Clock-Domain Crossing
Multi-Bit Mux-Select Synchronizer — L2 Upgrade
Cross-clock domain synchronizer for multi-bit select signals using Gray code encoding to prevent metastability glitches.
About this block
Simulate it in the Verilog IDE
Multi-Bit Mux-Select Synchronizer — L2 Upgrade is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.
This IP implements a safe cross-clock domain synchronizer for multi-bit selection signals. It converts binary select values to Gray code to prevent metastability-induced glitches during synchronization. The Gray-coded signal is synchronized using a two-stage flip-flop chain. The destination domain converts the Gray code back to binary. A separate two-stage synchronizer handles the valid signal handshake. This design ensures that the destination domain only sees stable, valid binary values.
This IP provides a robust solution for synchronizing multi-bit control signals across clock domains. It uses Gray coding to minimize transition errors during synchronization. The design is parameterizable for different select widths. Simulation confirms correct functionality for various input patterns.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Multi-Bit Mux-Select Synchronizer — L2 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: Cross-clock domain synchronizer for multi-bit select signals using Gray code encoding to prevent metastability glitches.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The module operates in three distinct stages:
- Source Domain Logic: Converts the binary select input to Gray code.
- Cross-Clock Domain Synchronization: Transfers the Gray code safely using a two-stage synchronizer.
- Destination Domain Logic: Converts the Gray code back to binary.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
clk_src | Input | 1 | Source clock domain |
rst_n_src | Input | 1 | Active-low reset for source domain |
sel_src | Input | SEL_WIDTH | Binary select input from source |
valid_src | Input | 1 | Valid signal from source domain |
clk_dst | Input | 1 | Destination clock domain |
rst_n_dst | Input | 1 | Active-low reset for destination domain |
sel_dst | Output | SEL_WIDTH | Synchronized binary select output |
valid_dst | Output | 1 | Synchronized valid output |
Verification
The testbench validates:
- Reset behavior.
- Multiple select values (e.g., 1, 7, 10, 15).
- Valid signal propagation and drop conditions.
All test cases passed successfully in simulation, confirming correct functionality for various input patterns.
More in Clock-Domain Crossing
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- Single-Cycle Pulse Synchronizer (2-FF + Edge Detector)
- Slow-Enable Fast Sample-Hold