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Clock-Domain Crossing

Slow-Enable Fast Sample-Hold

Samples data on a rising edge of a synchronized slow enable signal in a fast clock domain.

Open in IDE Category Wiki · CDC

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

Slow-Enable Fast Sample-Hold is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a cross-clock-domain sample-and-hold circuit. It operates in the clk_fast domain, capturing data from data_in based on a synchronized, slow enable signal (en_slow_raw).

The design ensures metastability safety using a two-stage synchronizer chain. The sampled data is held in data_out until the next enable edge. This module is suitable for interfacing low-frequency control signals with high-speed data paths.

This IP provides a robust method for sampling high-speed data using a low-frequency enable signal. By synchronizing the enable signal across clock domains, it prevents metastability issues while maintaining data integrity. The design is simple, using a two-stage synchronizer and a standard sample-and-hold logic, making it easy to integrate into larger systems requiring cross-clock-domain control.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Slow-Enable Fast Sample-Hold.
  2. Read the Verilog module in the editor. The catalog line for this block: Samples data on a rising edge of a synchronized slow enable signal in a fast clock domain.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port NameDirectionWidthDescription
clk_fastinput1Fast clock domain
rst_ninput1Active-low asynchronous reset
clk_slowinput1Slow clock domain (reference only, not used internally)
en_slow_rawinput1Raw slow enable signal from slow domain
data_ininput[7:0]Data to be sampled
data_outoutput[7:0]Sampled and held data

Verification

The provided testbench (tb/tb_slow_enable_fast_sample_hold.v) validates the following behaviors:

  1. Reset Behavior: Ensures data_out initializes to zero.
  2. Hold State: Verifies output remains constant when en_slow_raw is inactive.
  3. Sampling: Confirms data_out updates to data_in on the rising edge of the synchronized enable.
  4. Multiple Samples: Checks correct operation across multiple enable cycles.

### Expected Simulation Results

Upon running the simulation, the log should display:

  • TC1 PASS - Reset state correct
  • TC2 PASS - Hold state correct
  • TC3 PASS - Sample correct
  • TC4 PASS - Hold correct
  • TC5 PASS - Second sample correct
  • TC6 PASS - Reset correct
  • INFO: PASS

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