Clock-Domain Crossing

Asynchronous Reset Synchronizer for FIFO Gray Pointer Crossings

2-stage asynchronous reset synchronizer chain for safe Gray-coded FIFO pointer synchronization across clock domains with active-low reset handling.

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Asynchronous Reset Synchronizer for FIFO Gray Pointer Crossings is a SystemVerilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a 2-stage asynchronous reset synchronizer chain optimized for safe reset handling across clock domains when synchronizing Gray-coded FIFO pointers. It ensures metastability resolution while preserving reset integrity during assertion and deassertion. The design separates asynchronous reset handling in the source domain from synchronous reset handling in the destination domain to meet CDC best practices. The synchronizer chain consists of two registers in the destination domain, with the first stage capturing data from the source domain and the second stage providing final synchronized output. Reset is active-low and asynchronous in the source domain, while synchronous in the destination domain—ensuring deterministic reset release timing. The module supports configurable Gray pointer width (minimum 2 bits) and is compatible with standard CDC verification flows. It follows lowRISC/ibex CDC infrastructure conventions and is suitable for integration into asynchronous FIFOs, handshake protocols, or cross-domain control logic. The testbench validates reset timing, metastability resolution, and Gray code transitions under multi-clock conditions. All test cases pass successfully, confirming safe reset propagation and pointer synchronization. The implementation is synthesizable and verified with Verilator.

The async_reset_fifo_sync IP provides a robust, synthesizable solution for synchronizing Gray-coded pointers across asynchronous reset boundaries. Its dual-domain reset handling (asynchronous source, synchronous destination) prevents reset-induced glitches and metastability propagation. Designed for FIFO pointer synchronization, it integrates seamlessly into CDC-critical paths and aligns with open-source IP standards. Integrators should ensure WIDTH ≥ 2, align reset deassertion timing with CDC guidelines, and verify timing closure across domains.

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Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
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Ports

Name	Direction	Type	Description
`clk_src`	input	logic	Source clock domain (asynchronous reset domain)
`rst_n_src`	input	logic	Asynchronous active-low reset in source domain
`d_in`	input	logic [WIDTH-1:0]	Gray-coded pointer value from source domain
`q_out`	output	logic [WIDTH-1:0]	Synchronized gray pointer in destination domain
`clk_dst`	input	logic	Destination clock domain
`rst_n_dst`	input	logic	Synchronous active-low reset in destination domain

Verification

Test Case	Description	Status
TC1	Reset assertion during stable input	PASS
TC2	Reset deassertion with metastability handling	PASS
TC3	Gray pointer transitions (0→1→3→2→6→7→5→4)	PASS
TC4	Reset asserted mid-pointer transition	PASS

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