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Clock-Domain Crossing

Enable Level Synchronizer — L1 Upgrade

Enable Level Synchronizer with Busy Hold for CDC

Open in IDE Category Wiki · CDC

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Enable Level Synchronizer — L1 Upgrade is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This Intellectual Property (IP) implements an enable-level synchronizer with a busy-hold mechanism. It safely crosses a single-bit enable signal between two asynchronous clock domains. The module ensures that the destination enable signal is stable before deasserting, preventing glitches and metastability issues common in Clock Domain Crossing (CDC) scenarios.

Key features include:

  • 3-Stage Synchronizer Chain: Mitigates metastability for the enable signal.
  • Busy-Hold Logic: Prevents premature deassertion of downstream logic by holding the busy flag until the deassertion is fully synchronized.
  • Asynchronous Reset: Supports active-low asynchronous reset for safe initialization.

This IP provides a robust enable-level synchronizer with a busy-hold mechanism, suitable for L1 upgrade scenarios requiring reliable clock domain crossing. It uses a 3-stage synchronizer chain to mitigate metastability and a busy flag to ensure downstream logic sees a clean transition. The design has been verified through comprehensive simulation covering idle, assertion, deassertion, and reset behaviors.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Enable Level Synchronizer — L1 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Enable Level Synchronizer with Busy Hold for CDC.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The core design consists of two main components:

  1. Synchronizer Chain: A 3-stage flip-flop chain registered on the destination clock (clk_dst) to synchronize the source enable (en_src).
  2. Busy Logic: Monitors the source enable and the synchronized output. The busy signal is asserted when en_src is high and remains high until the synchronized output (en_dst) goes low AND the previous source state was low. This ensures the downstream logic has fully processed the enable pulse.

Ports

Port NameDirectionWidthDescription
clk_srcInput1Source clock domain
clk_dstInput1Destination clock domain
rst_nInput1Active-low asynchronous reset
en_srcInput1Source enable signal to be synchronized
en_dstOutput1Synchronized destination enable signal
busyOutput1Busy flag: High during synchronization/holding

Constraints

  • Clock Domains: clk_src and clk_dst must be asynchronous. No specific frequency ratio is required, but the destination clock should be fast enough to capture the synchronized signal.
  • Reset: rst_n is asynchronous and active-low. Ensure reset is deasserted before enabling signals.
  • Timing: The busy hold logic ensures en_dst is stable. No additional SDC/XDC constraints are strictly required for CDC, but standard CDC constraints (false paths, multicycle paths) may be applied if needed by your synthesis tool.

Verification

The provided testbench (tb_enable_level_sync_busy_hold.v) validates the following scenarios:

  • Idle State: Verifies en_dst and busy are low when en_src is low.
  • Assertion: Verifies en_dst goes high after propagation delay and busy is asserted.
  • Deassertion: Verifies busy remains high until en_dst goes low, ensuring safe handshaking.
  • Reset: Verifies all outputs are forced to low upon reset.

To verify the IP, run the simulation script provided in the sim directory. The testbench will output a summary of passed test cases.

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