Clock-Domain Crossing

Req/Ack Payload Hold 8-bit

Asynchronous clock domain crossing module for 8-bit payloads using Req/Ack handshake with backpressure.

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About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

Req/Ack Payload Hold 8-bit is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a robust Clock Domain Crossing (CDC) interface for 8-bit payloads using a Request/Acknowledge (Req/Ack) handshake protocol. It ensures data integrity between asynchronous clock domains (clk_src and clk_dst) by holding the payload stable in the source domain until the destination acknowledges receipt.

The design includes synchronizer chains to handle metastability and backpressure logic to prevent data loss during high traffic. It is suitable for low-throughput, high-reliability data transfer scenarios where data must not be overwritten before consumption.

The core functionality involves:

Source Domain: Captures data_in on a req_in pulse. The data is held in a register until an acknowledgment is received from the destination.
Destination Domain: Detects the request, captures the data, and sends back an acknowledgment.
Synchronization: Two-stage synchronizer chains are used for control signals crossing clock domains to mitigate metastability risks.
Backpressure: The source ignores new requests while a transaction is pending (payload_valid is high), ensuring no data is overwritten before being consumed.

Choose Open in IDE. RTL Studio loads the packaged workspace for Req/Ack Payload Hold 8-bit.
Read the Verilog module in the editor. The catalog line for this block: Asynchronous clock domain crossing module for 8-bit payloads using Req/Ack handshake with backpressure.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Asynchronous CDC: Safe data transfer between clk_src and clk_dst.
8-bit Payload: Supports 8-bit data width with stability guarantees.
Metastability Protection: Synchronizer chains for req and ack signals.
Backpressure: Prevents data loss by blocking new requests during pending transactions.
Verified: Validated via Icarus Verilog simulation with comprehensive test cases.

Ports

Port Name	Direction	Width	Description
`clk_src`	Input	1	Source domain clock
`rst_n_src`	Input	1	Source domain active-low reset
`data_in`	Input	[7:0]	Input data payload
`req_in`	Input	1	Request signal from source (pulse)
`ack_out`	Output	1	Acknowledge to source (indicates data is held valid in src)
`clk_dst`	Input	1	Destination domain clock
`rst_n_dst`	Input	1	Destination domain active-low reset
`data_out`	Output	[7:0]	Output data payload
`req_out`	Output	1	Request signal to destination
`ack_in`	Input	1	Acknowledge from destination

Architecture

The design is divided into two main domains:

Source Domain Logic:

- Holds data_in in payload_reg when req_in is asserted. - Asserts ack_out to indicate data is held. - Clears payload_valid upon receiving synchronized acknowledgment.

Destination Domain Logic:

- Synchronizes req_in to clk_dst. - Latches data_out when request is detected. - Generates ack_in to signal completion.

Verification

The testbench validates:

Basic Handshake: Single byte transfer.
Sequence Transfer: Multiple bytes in sequence.
Backpressure: Ensures data is held stable if the destination is busy.
Ack Integrity: Verifies ack_out toggles correctly.

### Running Simulation

To run the simulation:

Ensure Icarus Verilog is installed.
Run the provided testbench script.
Check the log for INFO: PASS.

### Test Results

Test Case	Description	Result
TC1	Basic Handshake Single Byte	PASS
TC2	Multiple Bytes Sequence	PASS
TC3	Backpressure Hold Stability	PASS
TC4	Ack Out Integrity	PASS

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