Clock-Domain Crossing

Dual-Clock Pulse with Credit Return

Dual-clock domain crossing for single-cycle pulses with credit-based flow control.

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Dual-Clock Pulse with Credit Return is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This Intellectual Property (IP) provides a robust solution for crossing single-cycle pulses between asynchronous clock domains. It utilizes a credit-based flow control mechanism to guarantee that the sender does not overflow the receiver, ensuring reliable communication for high-frequency control signals.

The design employs two-stage synchronizers for both data and acknowledgment paths to mitigate metastability risks. It is suitable for scenarios where a single-cycle pulse in one domain must trigger a single-cycle pulse in the other, with back-pressure to prevent data loss.

This IP provides a robust solution for crossing single-cycle pulses between asynchronous clock domains. It utilizes a credit-based flow control mechanism to guarantee that the sender does not overflow the receiver, ensuring reliable communication for high-frequency control signals. The design employs two-stage synchronizers for both data and acknowledgment paths to mitigate metastability risks.

Choose Open in IDE. RTL Studio loads the packaged workspace for Dual-Clock Pulse with Credit Return.
Read the Verilog module in the editor. The catalog line for this block: Dual-clock domain crossing for single-cycle pulses with credit-based flow control.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Metastability Protection: Two-stage synchronizers on both forward and return paths.
Flow Control: Credit-based mechanism ensures the source waits for acknowledgment before sending the next pulse.
Single-Cycle Pulse: Generates a clean, single-cycle output pulse in the destination domain.
Independent Resets: Separate active-low resets for source and destination domains.

Architecture

The design consists of three main stages: synchronization, edge detection, and credit return.

Source Domain: The input pulse is registered to align with src_clk.
Destination Domain: The signal is synchronized using a two-stage flip-flop chain clocked by dst_clk. A rising edge detector generates a single-cycle output pulse.
Credit Return: An acknowledgment signal is generated in the destination domain and synchronized back to the source domain. The source domain uses this credit to gate further pulse transmissions, ensuring the receiver is ready.

Ports

Port Name	Direction	Width	Description
src_clk	Input	1	Source clock domain
src_rst_n	Input	1	Active-low reset for source domain
pulse_in	Input	1	Single-cycle pulse input
dst_clk	Input	1	Destination clock domain
dst_rst_n	Input	1	Active-low reset for destination domain
pulse_out	Output	1	Synchronized single-cycle pulse output
credit_ready	Output	1	High when source is allowed to send next pulse

Integration

### Instantiation Example

### Constraints

Pulse Width: pulse_in must be at least one src_clk cycle wide.
Spacing: The source must wait for credit_ready to go high before asserting pulse_in again.
Clock Domains: Ensure proper SDC constraints for src_clk and dst_clk as asynchronous domains.

Verification

The testbench verifies reset behavior, single pulse transmission, and back-to-back pulse handling. All tests pass successfully with zero errors.

Test Case	Description	Result
TC1	Reset state validation	PASS
TC2	Single pulse propagation	PASS
TC3	Back-to-back pulse flow control	PASS

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