Clock-Domain Crossing

Handshake CDC with 8-Bit Payload

Reliable asynchronous clock domain crossing using a two-way handshake protocol for 8-bit data payloads.

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About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

Handshake CDC with 8-Bit Payload is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a robust, latch-free Clock Domain Crossing (CDC) mechanism for transferring 8-bit parallel data between asynchronous clock domains. It utilizes a two-way handshake protocol (Request/Acknowledge) to ensure data integrity and prevent metastability. The design is fully synthesizable for both FPGA and ASIC flows and includes synchronized request and acknowledge signals.

This IP provides a robust, latch-free solution for 8-bit data transfer across asynchronous clock domains.

By utilizing a two-way handshake with synchronized request and acknowledge signals, it ensures data integrity and prevents metastability issues.

Choose Open in IDE. RTL Studio loads the packaged workspace for Handshake CDC with 8-Bit Payload.
Read the Verilog module in the editor. The catalog line for this block: Reliable asynchronous clock domain crossing using a two-way handshake protocol for 8-bit data payloads.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-Bit Parallel Data Transfer: Supports transfer of 8-bit data words.
Two-Way Handshake: Uses a robust request/acknowledge protocol for flow control.
Metastability Mitigation: Includes 2-stage synchronizers for both req and ack signals.
Reset Handling: Handles asynchronous reset conditions in both source and destination domains.
Edge Detection: Provides clear rise and fall edge detection for handshake timing control.
Latch-Free Design: Ensures predictable timing and synthesizability.

Interface

The module operates with the following ports:

Port Name	Direction	Width	Description
`src_clk`	Input	1	Source clock domain
`src_rst_n`	Input	1	Active-low source reset
`dst_clk`	Input	1	Destination clock domain
`dst_rst_n`	Input	1	Active-low destination reset
`payload_in`	Input	8	Data to be transferred
`req`	Input	1	Request signal from source
`ack`	Output	1	Acknowledge signal from destination
`payload_out`	Output	8	Received data in destination

Architecture

The handshake protocol follows a strict four-step sequence to ensure safe data transfer:

Request: The source asserts req and drives payload_in.
Acknowledge: The destination detects the synchronized req, asserts ack, and latches payload_in.
Deassert Request: The source detects the synchronized ack and deasserts req.
Deassert Acknowledge: The destination detects the deassertion of req and deasserts ack.

### Signal Flow

The following diagram illustrates the signal flow and synchronization stages:

Verification

The design is verified using a testbench (tb/tb_handshake_cdc_payload_8bit.v) that covers three primary scenarios:

Test Case	Description	Expected Result
TC1	Basic single transfer	Payload matches expected value
TC2	Multiple transfers	All payloads transferred correctly
TC3	Rapid successive transfers	No data loss or corruption

### Running Simulation

To verify the design:

Open your preferred HDL simulator.
Load the testbench file: tb/tb_handshake_cdc_payload_8bit.v.
Run the simulation.
Check the log panel for the following output:

- TC1 PASS - TC2 PASS - TC3 PASS - Simulation ends with INFO: PASS.

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