Clock-Domain Crossing

Single-Cycle Pulse Synchronizer (2-FF + Edge Detector)

Transfers a single-clock-cycle pulse across asynchronous clock domains using a 2-FF synchronizer, edge detector, and pulse stretcher. Supports clock ratios up to 10:1 and variable reset polarity.

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About this block

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Mediumsystemverilogsimsyn

Single-Cycle Pulse Synchronizer (2-FF + Edge Detector) is a SystemVerilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP transfers a single-clock-cycle pulse from a source clock domain (src_clk) to a destination clock domain (dst_clk). It uses a two-stage synchronizer (two flip-flops) to mitigate metastability, followed by an edge detector and pulse stretcher to ensure reliable single-cycle pulse generation in the destination domain. It supports variable clock ratios up to 10:1 and handles asynchronous resets with configurable polarity.

The pulse_sync_2ff IP provides a robust, synthesizable solution for single-cycle pulse transfer across asynchronous clock domains. It combines metastability-hardened synchronization with edge detection and pulse stretching to ensure reliable one-cycle pulse delivery in the destination domain, even under aggressive clock ratios and timing races. Integrators should verify clock phase relationships and pulse timing in their system context, especially when src_clk and dst_clk are not phase-aligned. The design is lightweight (6 FFs), easy to integrate, and thoroughly verified across common edge cases.

Choose Open in IDE. RTL Studio loads the packaged workspace for Single-Cycle Pulse Synchronizer (2-FF + Edge Detector).
Read the SystemVerilog module in the editor. The catalog line for this block: Transfers a single-clock-cycle pulse across asynchronous clock domains using a 2-FF synchronizer, edge detector, and pulse stretcher. Supports clock ratios up to 10:1 and variable reset polarity.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Parameters

Parameter	Type	Default	Description
`ASYNC_RST_POL`	int	1	Reset polarity: `1` = active-high, `0` = active-low

> Note: Ports use _n suffix (e.g., src_rst_n) to indicate active-*low* signals, regardless of ASYNC_RST_POL. The parameter controls internal reset assertion logic.

Ports

Name	Direction	Type	Description
`src_rst_n`	input	logic	Asynchronous reset (active-low) in source domain
`dst_rst_n`	input	logic	Asynchronous reset (active-low) in destination domain
`src_clk`	input	logic	Source clock domain
`dst_clk`	input	logic	Destination clock domain
`src_pulse_i`	input	logic	Single-cycle pulse in `src_clk` (must be asserted for exactly one cycle)
`dst_pulse_o`	output	logic	Single-cycle pulse in `dst_clk`

Integration

The synchronizer is *edge-triggered*; continuous or multi-cycle pulses in src_clk will be converted to a single-cycle pulse in dst_clk.
Reset is asynchronous and active-*low* by convention (use _n signals). Configure polarity via ASYNC_RST_POL.
For best reliability, avoid very high clock ratios (>10:1) without additional timing validation.
In FPGA flows, consider constraining the synchronizer path with set_multicycle_path or similar if needed.

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