Clock-Domain Crossing
3-Stage Asynchronous Reset Synchronizer
Synchronizes an asynchronous active-low reset signal to a synchronous clock domain using a 3-stage flip-flop chain to minimize metastability.
About this block
Simulate it in the Verilog IDE
3-Stage Asynchronous Reset Synchronizer is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP provides a robust mechanism to synchronize an asynchronous active-low reset signal (async_reset_n) to a synchronous clock domain (clk). It utilizes a chain of three D flip-flops to minimize the risk of metastability during state transitions. The design ensures that the asynchronous reset is reliably propagated through the clock domain boundary. Glitches shorter than one clock period are filtered out by the synchronizer chain.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 3-Stage Asynchronous Reset Synchronizer.
- Read the Verilog module in the editor. The catalog line for this block: Synchronizes an asynchronous active-low reset signal to a synchronous clock domain using a 3-stage flip-flop chain to minimize metastability.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The core logic consists of three cascaded flip-flops registered on the positive edge of the clock. Each stage receives an asynchronous active-low reset input to force a known low state immediately. The output of the third stage drives the sync_reset_n signal. This topology guarantees that the output changes only on clock edges after the reset deassertion.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Synchronous clock signal for the destination domain. |
| async_reset_n | Input | 1 | Asynchronous active-low reset signal from the source domain. |
| sync_reset_n | Output | 1 | Synchronized active-low reset signal for the destination domain. |
Verification
The testbench validates three primary scenarios to ensure functional correctness:
- Reset Deassertion: Verifies that the output goes low during reset and rises after deassertion.
- Assertion During Operation: Confirms that asserting reset while the system is running forces the output low.
- Glitch Immunity: Demonstrates immunity by applying a pulse shorter than one clock cycle.
All tests passed successfully in the Icarus Verilog simulation environment.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Reset Deassertion Synchronization | PASS |
| TC2 | Reset Assertion During Operation | PASS |
| TC3 | Glitch Immunity | PASS |
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