Clock-Domain Crossing

Four-Phase Req/Ack CDC Payload 16-bit

A 16-bit cross-domain clock synchronizer using a four-phase handshake protocol with backpressure support.

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About this block

Simulate it in the Verilog IDE

Hardverilogsimsyn

Four-Phase Req/Ack CDC Payload 16-bit is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a robust 16-bit data transfer across asynchronous clock domains using a four-phase handshake protocol. It ensures data integrity and flow control through explicit valid/ready handshakes synchronized via 3-stage synchronizers.

Key Highlights:

Protocol: Four-phase request/acknowledge handshake.
Data Width: 16-bit payload.
Flow Control: Supports backpressure via ready_in and ready_out.
Safety: Metastability hardened with 3-stage synchronizers for both request and acknowledge paths.
Reset: Asynchronous reset support in both source and destination domains.

Choose Open in IDE. RTL Studio loads the packaged workspace for Four-Phase Req/Ack CDC Payload 16-bit.
Read the Verilog module in the editor. The catalog line for this block: A 16-bit cross-domain clock synchronizer using a four-phase handshake protocol with backpressure support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

16-bit Payload: Configurable data width (currently fixed at 16 bits).
Four-Phase Handshake: Ensures reliable synchronization between source and destination domains without data loss.
Backpressure Support: Gracefully handles flow control via ready_in (source side) and ready_out (destination side).
Asynchronous Reset: Fully supports asynchronous resets (rst_n_src, rst_n_dst) in both clock domains.
Metastability Hardened: Uses 3-stage synchronizers for req_src and ack_dst signals to safely cross clock domains.

Ports

Port Name	Direction	Width	Description
`clk_src`	Input	1	Source clock domain
`rst_n_src`	Input	1	Source asynchronous reset (active low)
`data_in`	Input	16	Input data payload
`valid_in`	Input	1	Source valid signal (data is valid)
`ready_in`	Output	1	Source ready signal (backpressure from this IP)
`clk_dst`	Input	1	Destination clock domain
`rst_n_dst`	Input	1	Destination asynchronous reset (active low)
`data_out`	Output	16	Output data payload
`valid_out`	Output	1	Destination valid signal (data is valid)
`ready_out`	Input	1	Destination ready signal (backpressure from downstream)

Architecture

The module uses two Finite State Machines (FSMs) to manage the handshake. One FSM operates in the source clock domain, and the other in the destination clock domain. Synchronization registers bridge the two domains.

Operation Flow:

The Source FSM asserts req_src when valid_in and ready_in are high.
The Destination FSM detects req_sync_3 and asserts ack_dst.
The Destination FSM holds ack_dst until ready_out is asserted by the downstream consumer.
The Source FSM detects ack_sync_3 and deasserts req_src, completing the cycle.

Integration

### Instantiation

### Constraints (SDC)

Ensure proper clock domain crossing constraints are applied in your design. Note that specific cell names may vary based on synthesis; adjust the get_cells patterns accordingly.

Verification

The testbench verifies single transfers, multiple transfers, and backpressure scenarios. All test cases passed successfully in the simulation log.

Test Case	Description	Result
TC1	Single Transfer	PASS
TC2	Multiple Transfers	PASS
TC3	Backpressure	PASS

### Running Simulation

To verify the design:

Open the project in your preferred HDL simulator.
Run the testbench tb_four_phase_req_ack_payload_16.
Check the log for the following output:

- TC1 PASS - Data matched - TC2 PASS - Last data matched - TC3 PASS - Ready_in deasserted - TC3 PASS - Data matched after backpressure - Simulation ends with INFO: PASS.

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