Clock-Domain Crossing

4-Bit Bus Synchronizer (2-FF per bit)

A 4-bit bus synchronizer using a two-stage flip-flop per bit to safely transfer asynchronous signals into a synchronous domain.

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About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

4-Bit Bus Synchronizer (2-FF per bit) is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a robust 4-bit bus synchronizer using a two-stage flip-flop per bit architecture. It safely transfers asynchronous or multi-bit bus signals from one clock domain to another, preventing metastability propagation. The design ensures that all bits are synchronized independently, making it suitable for crossing clock domains with low frequency ratios or asynchronous inputs.

Important Usage Note: This synchronizer is safe for single-bit signals or multi-bit buses that change slowly (i.e., the bus value remains stable for at least 2-3 clock cycles of the destination domain). For rapidly changing multi-bit buses, consider using a Gray code encoder or a FIFO.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Bit Bus Synchronizer (2-FF per bit).
Read the Verilog module in the editor. The catalog line for this block: A 4-bit bus synchronizer using a two-stage flip-flop per bit to safely transfer asynchronous signals into a synchronous domain.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module consists of two registers per bit in the destination clock domain (clk_dst).

Stage 1: Captures the asynchronous input on the destination clock edge.
Stage 2: Captures the first stage output to ensure stability before driving the final output bus.

This structure minimizes the probability of metastability reaching downstream logic. Each bit is synchronized independently to avoid issues associated with multi-bit handshakes.

Ports

Port Name	Direction	Width	Description
clk_dst	Input	1	Destination clock domain
rst_n	Input	1	Active-low synchronous reset
async_bus	Input	4	Asynchronous input bus
sync_bus	Output	4	Synchronized output bus

Verification

The testbench validates reset behavior and data synchronization. It checks single-bit transitions, multi-bit pattern changes, and random patterns to ensure robustness. All test cases pass successfully in simulation.

Test Case	Description	Result
TC1	Reset Check	PASS
TC2	Single Bit Transition	PASS
TC3	Multi-Bit Transition	PASS
TC4	Transition to Zero	PASS
TC5	Random Pattern Check	PASS

### Expected Simulation Results

After Run Simulation, the Log panel should show:

TC1 PASS - Reset check passed
TC2 PASS - Sync check passed for 0001
TC3 PASS - Sync check passed for 1111
TC4 PASS - Sync check passed for 0000
TC5 PASS - Sync check passed for 1010
INFO: PASS

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