Clock-Domain Crossing
Pulse-Ack Round-Trip Across 2 Clocks
Implements a pulse-acknowledgment round-trip mechanism across two asynchronous clock domains to ensure reliable single-cycle pulse transmission and acknowledgment.
About this block
Simulate it in the Verilog IDE
Pulse-Ack Round-Trip Across 2 Clocks is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP implements a robust pulse-acknowledgment round-trip mechanism for crossing single-cycle pulses between two asynchronous clock domains. It ensures reliable data transmission by using double-flop synchronizers on both the forward (source to destination) and reverse (acknowledgment) paths, effectively mitigating metastability risks.
This module provides a simple, low-latency handshake protocol for asynchronous clock domains. It is ideal for applications requiring simple event signaling without the overhead of complex protocols like AXI or Wishbone. Key benefits include:
- Metastability Protection: Uses standard double-flop synchronizers.
- Back-to-Back Pulse Handling: Correctly handles consecutive pulses without loss or spurious detection.
- Minimal Overhead: Small area footprint and low latency.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Pulse-Ack Round-Trip Across 2 Clocks.
- Read the Verilog module in the editor. The catalog line for this block: Implements a pulse-acknowledgment round-trip mechanism across two asynchronous clock domains to ensure reliable single-cycle pulse transmission and acknowledgment.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- Supports single-cycle pulse transmission from source to destination.
- Provides an acknowledgment pulse back to the source domain upon successful reception.
- Handles back-to-back pulses without loss or spurious detection.
- Includes reset synchronization for both clock domains.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
src_clk | Input | 1 | Source clock domain |
dst_clk | Input | 1 | Destination clock domain |
src_rst_n | Input | 1 | Active-low reset for source domain |
dst_rst_n | Input | 1 | Active-low reset for destination domain |
src_pulse_in | Input | 1 | Input pulse from source domain (must be synchronized) |
dst_pulse_out | Output | 1 | Output pulse in destination domain |
dst_ack_out | Output | 1 | Acknowledgment pulse back to source domain |
Verification
The testbench verifies the following scenarios:
| Test Case | Description | Result |
|---|---|---|
| TC1 | Single pulse transmission and acknowledgment | PASS |
| TC2 | Back-to-back pulses handling | PASS |
| TC3 | No spurious pulses after settling | PASS |
All tests passed successfully in simulation.
More in Clock-Domain Crossing
- 1-Bit Handshake CDC Bridge
- 3-Stage Asynchronous Reset Synchronizer
- 4-Bit Bus Synchronizer (2-FF per bit)
- 4-Bit Gray Bus Synchronizer — L2 Upgrade
- Async Handshake Pulse Bridge
- Async Set Sync-Clear Flag — L2 Upgrade
- Asynchronous Reset Synchronizer for FIFO Gray Pointer Crossings
- Dual-Clock Pulse with Credit Return
- Enable Level Synchronizer — L1 Upgrade
- Four-Phase Req/Ack CDC Payload 16-bit
- Handshake CDC with 8-Bit Payload
- Multi-Bit Bus Synchronizer (2-FF)
- Multi-Bit Mux-Select Synchronizer — L2 Upgrade
- Req/Ack Payload Hold 8-bit
- Single-Cycle Pulse Synchronizer (2-FF + Edge Detector)
- Slow-Enable Fast Sample-Hold