Clock-Domain Crossing

Multi-Bit Bus Synchronizer (2-FF)

Synchronizes an 8-bit bus using a two-flop synchronizer chain per bit — educational follow-on to single-bit two_ff_sync.

Open in IDE Category Wiki · CDC

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

Multi-Bit Bus Synchronizer (2-FF) is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This module implements a two-flop synchronizer chain for each bit of a multi-bit bus (data_in) to transfer data from a source clock domain to a destination clock domain (clk_dst). It uses an active-low asynchronous reset (rst_n_dst) and an enable signal (en_in) to control data capture.

WARNING: This synchronizer resolves metastability on a per-bit basis. It does not guarantee that the multi-bit value remains valid during the transition. For multi-bit data, this method is only safe if the data changes slowly enough or if combined with a handshake protocol. For high-speed or critical multi-bit transfers, Gray coding or FIFOs are recommended.

The bus_sync_2ff module captures data_in on the rising edge of clk_dst when en_in is asserted. The signal passes through two sequential registers in the destination clock domain. This structure provides sufficient time for metastability to resolve before the output is sampled by downstream logic.

Metastability Resolution: Each bit is synchronized independently.
Latency: The output data_out is valid 2 cycles after en_in is asserted (assuming en_in is synchronous to clk_dst or properly timed).
Reset: Asynchronous active-low reset clears both stages.

Choose Open in IDE. RTL Studio loads the packaged workspace for Multi-Bit Bus Synchronizer (2-FF).
Read the Verilog module in the editor. The catalog line for this block: Synchronizes an 8-bit bus using a two-flop synchronizer chain per bit — educational follow-on to single-bit two_ff_sync.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk_dst`	Input	1	Destination clock domain. Rising edge sensitive.
`rst_n_dst`	Input	1	Active-low asynchronous reset. Resets both sync stages.
`en_in`	Input	1	Enable signal. When high, `data_in` is captured into `sync_stage1`.
`data_in`	Input	[7:0]	Input data bus from source domain.
`data_out`	Output	[7:0]	Synchronized output data bus.

Verification

The testbench validates the following scenarios using Icarus Verilog:

Test Case	Description	Result
TC1	Basic Data Transfer	PASS
TC2	Reset Behavior	PASS
TC3	Enable Control	PASS
TC4	Random Patterns	PASS

Simulation Details:

Tool: Icarus Verilog
Waveform: VCD dump available for waveform analysis.
Coverage: Functional coverage includes reset, enable gating, and random data patterns.

More in Clock-Domain Crossing

All Clock-Domain Crossing blocks