Clock-Domain Crossing

Toggle Bus Capture 4-bit

Captures a 4-bit data bus synchronized to a destination clock domain using a toggle mechanism and 2-stage synchronizer.

Open in IDE Category Wiki · CDC

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Toggle Bus Capture 4-bit is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core captures a 4-bit data bus synchronized to a destination clock domain using a toggle mechanism.

It employs a 2-stage synchronizer on the valid_src signal to ensure metastability safety during cross-domain transfer.

The design guarantees data integrity when moving signals between asynchronous clock domains with low latency.

Choose Open in IDE. RTL Studio loads the packaged workspace for Toggle Bus Capture 4-bit.
Read the Verilog module in the editor. The catalog line for this block: Captures a 4-bit data bus synchronized to a destination clock domain using a toggle mechanism and 2-stage synchronizer.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
clk_src	Input	1	Source clock domain
clk_dst	Input	1	Destination clock domain
rst_n	Input	1	Active-low asynchronous reset
data_in	Input	[3:0]	4-bit data bus from source domain
valid_src	Input	1	Source valid signal (toggle flag)
data_out	Output	[3:0]	Captured 4-bit data in destination domain
valid_dst	Output	1	Destination valid pulse

Architecture

The design consists of a synchronizer chain and a capture logic block.

Synchronizer Stages: Align the source valid signal to the destination clock domain.
Edge Detection: Identifies the rising transition of the synchronized signal.
Capture Registers: Store the input data upon edge detection.

Verification

The testbench validates basic transfer, multiple transfers, and rapid successive transfers. All test cases passed successfully in the Icarus Verilog simulation environment.

Test Case	Description	Result
TC1	Basic single transfer	PASS
TC2	Multiple transfers with different data	PASS
TC3	Rapid successive transfers	PASS

### Expected Simulation Output

After running the simulation, the Log panel should show:

TC1 PASS - Data captured correctly
TC2 PASS - All transfers correct
TC3 PASS - Rapid transfers correct
Simulation ends with INFO: PASS.

More in Clock-Domain Crossing

All Clock-Domain Crossing blocks