Clock-Domain Crossing

Toggle Synchronizer 1-Bit — L2 Upgrade

Toggle synchronizer with 4-bit payload hold for asynchronous clock domain crossing.

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Hardverilogsimsyn

Toggle Synchronizer 1-Bit — L2 Upgrade is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a robust toggle-based synchronizer for crossing a single control bit between asynchronous clock domains, accompanied by a 4-bit payload hold mechanism. It ensures data integrity by capturing the payload in the source domain and releasing it in the destination domain only upon acknowledgment. The design utilizes a standard two-stage flip-flop chain for the control signal to mitigate metastability risks and employs a handshake protocol (valid/ready) to manage flow control.

This solution is ideal for L2 upgrade scenarios or any interface requiring safe data transfer across clock domains without losing payload information.

The module synchronizes a valid signal while holding the associated payload_data.

Metastability Protection: A two-stage synchronizer chain handles the control bit crossing.
Data Integrity: The payload is captured in the source domain when valid is asserted and ready_src is high. It remains stable until the destination acknowledges receipt.
Flow Control: The ready_src signal indicates to the source that the synchronizer is free to accept new data.

Choose Open in IDE. RTL Studio loads the packaged workspace for Toggle Synchronizer 1-Bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Toggle synchronizer with 4-bit payload hold for asynchronous clock domain crossing.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design consists of two main blocks:

Source Domain: Captures payload, asserts request, and waits for ready.
Destination Domain: Synchronizes the request, asserts valid, and acknowledges receipt.

### Block Diagram

Ports

Port Name	Direction	Width	Description
`clk_src`	Input	1	Source clock domain
`rst_n_src`	Input	1	Source asynchronous reset, active low
`payload_valid`	Input	1	Valid signal from source
`payload_data`	Input	4	Data payload from source
`ready_src`	Output	1	Ready signal to source (high when idle)
`clk_dst`	Input	1	Destination clock domain
`rst_n_dst`	Input	1	Destination asynchronous reset, active low
`payload_out`	Output	4	Data payload to destination
`valid_dst`	Output	1	Valid signal to destination

Verification

The testbench verifies basic payload transfer functionality across clock domains. It checks for correct data propagation for various input values and validates the ready_src signal behavior during idle states.

### Test Cases

Test Case	Description	Expected Result
TC1	Basic payload transfer	Payload passed correctly
TC2	Different payload value	Payload passed correctly
TC3	Zero payload	Payload passed correctly
TC4	Max payload	Payload passed correctly
TC5	Ready signal check	`ready_src` is high when idle

### Simulation Log

After running the simulation, the Log panel should confirm:

All test cases (TC1-TC5) pass.
Final status: Simulation ends with INFO: PASS.

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