Clock-Domain Crossing

Toggle CDC with 8-bit Payload Hold

Clock Domain Crossing module that transfers an 8-bit payload using a synchronized toggle signal for handshaking.

Open in IDE Category Wiki · CDC

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Toggle CDC with 8-bit Payload Hold is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This OpenIP implements a robust Clock Domain Crossing (CDC) module designed to transfer an 8-bit payload between two asynchronous clock domains.

It utilizes a synchronized toggle handshake mechanism to ensure data integrity. The design guarantees that the payload remains stable at the destination until the source acknowledges receipt, preventing data loss during rapid toggles or clock domain mismatches.

Choose Open in IDE. RTL Studio loads the packaged workspace for Toggle CDC with 8-bit Payload Hold.
Read the Verilog module in the editor. The catalog line for this block: Clock Domain Crossing module that transfers an 8-bit payload using a synchronized toggle signal for handshaking.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module operates on a request-acknowledge handshake protocol:

Source Side: The source captures the payload when a request toggle is detected. A double-flop synchronizer transfers the request signal to the destination clock domain safely.
Handshake: The destination detects the synchronized toggle and asserts an acknowledge signal. Simultaneously, it latches the payload.
Payload Hold: The source holds the payload valid until the destination's acknowledge signal is received. This ensures that if a new request occurs prematurely, the current data is not overwritten.

### Block Diagram

Interface

Signal Name	Direction	Width	Description
src_clk	Input	1	Source clock domain
src_rst_n	Input	1	Active-low reset for source
dst_clk	Input	1	Destination clock domain
dst_rst_n	Input	1	Active-low reset for destination
src_req	Input	1	Request signal to initiate transfer
src_payload	Input	8	Data payload to be transferred
dst_ack	Output	1	Acknowledge signal from destination
dst_payload	Output	8	Received data payload

Verification

The provided testbench (tb/tb_toggle_payload_hold_8.v) verifies the following scenarios:

Basic Transfer: Verifies single payload transfer with correct data integrity.
Subsequent Transfers: Checks handling of different payload values in sequential transfers.
Rapid Toggles: Ensures the design holds the first payload if a new request occurs before the previous one is acknowledged.

### Running the Simulation

To run the simulation, use your preferred Verilog simulator (e.g., Verilator, ModelSim, VCS). The testbench is located in tb/.

### Expected Results

TC1 PASS
TC2 PASS
TC3 PASS
INFO: PASS

Test Case	Description	Result
TC1	Basic single payload transfer	PASS
TC2	Second different payload transfer	PASS
TC3	Payload hold during rapid toggles	PASS

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