Clock-Domain Crossing

Toggle Synchronizer With Return Ack

Bidirectional toggle synchronizer with request and acknowledge paths for asynchronous clock domains.

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Hardverilogsimsyn

Toggle Synchronizer With Return Ack is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP core implements a robust, bidirectional handshake mechanism for transferring single-bit signals between two asynchronous clock domains (src_clk and dst_clk).

It utilizes standard two-stage synchronizer chains for both the request (forward) and acknowledge (return) paths to mitigate metastability risks.

The design ensures that a pulse asserted in the source domain is reliably detected in the destination domain, and the corresponding acknowledgment is safely returned to the source.

Choose Open in IDE. RTL Studio loads the packaged workspace for Toggle Synchronizer With Return Ack.
Read the Verilog module in the editor. The catalog line for this block: Bidirectional toggle synchronizer with request and acknowledge paths for asynchronous clock domains.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Bidirectional Handshaking: Supports full-duplex signaling with separate request and acknowledge paths.
Metastability Hardening: Each path employs a two-stage synchronizer (flip-flop chain) to reduce the probability of metastability to acceptable levels.
Asynchronous Reset: Both clock domains support independent asynchronous active-low resets (src_rst_n, dst_rst_n).
Simple Interface: Minimal pin count with single-bit inputs and outputs.
Pulse-Safe: Designed to handle single-cycle pulses or level-sensitive signals provided the user adheres to the handshake protocol (deasserting request before receiving ack).

Ports

Port Name	Direction	Width	Description
`src_clk`	Input	1	Source clock domain
`src_rst_n`	Input	1	Source asynchronous reset (active low)
`dst_clk`	Input	1	Destination clock domain
`dst_rst_n`	Input	1	Destination asynchronous reset (active low)
`req_in`	Input	1	Request signal from source domain (pulse or level)
`req_out`	Output	1	Synchronized request signal in destination domain
`ack_in`	Input	1	Acknowledge signal from destination domain
`ack_out`	Output	1	Synchronized acknowledge signal in source domain

Architecture

The design comprises two independent synchronizer chains operating in opposite directions.

Request Path (Source to Destination):

- req_in is registered in the src_clk domain to create a stable signal (req_reg). - req_reg is synchronized into the dst_clk domain using two flip-flops (req_sync1, req_sync2). - req_out is driven by the second stage of the synchronizer.

Acknowledge Path (Destination to Source):

- ack_in is registered in the dst_clk domain to create a stable signal (ack_reg). - ack_reg is synchronized into the src_clk domain using two flip-flops (ack_sync1, ack_sync2). - ack_out is driven by the second stage of the synchronizer.

Verification

The provided testbench validates the core functionality of the synchronizer.

Test Case	Description	Result
TC1	Reset Behavior	PASS
TC2	Single Request Pulse Propagation	PASS
TC3	Acknowledge Path Reverse Propagation	PASS
TC4	No Double Firing / Glitch Immunity	PASS

### Expected Simulation Output After running the simulation (e.g., using iverilog and vvp), the log should contain:

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