Clock-Domain Crossing
Two-Flip-Flop Synchronizer Chain — L1 Upgrade
Two-flip-flop CDC synchronizer with async reset stretching for source and destination domains.
About this block
Simulate it in the Verilog IDE
Two-Flip-Flop Synchronizer Chain — L1 Upgrade is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP implements a two-flip-flop synchronizer with async reset stretching. It safely transfers a single-bit signal between two asynchronous clock domains. The reset logic stretches the reset assertion if either source or destination domain is resetting. This prevents metastability propagation during reset deassertion.
The module synchronizes din from clk_src to clk_dst. It uses two flip-flops registered on clk_dst. Both flip-flops are cleared by a stretched reset signal. The stretched reset is active low and derived from rst_n_src AND rst_n_dst. This ensures the synchronizer is fully reset when either domain is in reset.
This IP provides a robust two-FF synchronizer with domain-independent reset stretching. It is suitable for L1 integration where simple CDC is required. Simulation confirms correct behavior under various reset and data transition scenarios. Use the VCD dump for detailed signal inspection.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Two-Flip-Flop Synchronizer Chain — L1 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: Two-flip-flop CDC synchronizer with async reset stretching for source and destination domains.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| clk_src | Input | 1 | Source clock domain |
| clk_dst | Input | 1 | Destination clock domain |
| rst_n_src | Input | 1 | Active-low reset for source domain |
| rst_n_dst | Input | 1 | Active-low reset for destination domain |
| din | Input | 1 | Data input from source domain |
| dout | Output | 1 | Synchronized data output |
Verification
The testbench verifies reset stretching and data propagation. It uses Icarus Verilog for simulation. VCD dump is enabled for waveform analysis.
| Test Case | Description | Expected Result | Status |
|---|---|---|---|
| TC1 | Reset Stretch | Output stays 0 when only dst reset is asserted | PASS |
| TC2 | Propagation 0->1 | Output becomes 1 after 3 dst cycles | PASS |
| TC3 | Propagation 1->0 | Output becomes 0 after 3 dst cycles | PASS |
| TC4 | Async Reset | Output clears to 0 when src reset is asserted | PASS |
More in Clock-Domain Crossing
- 1-Bit Handshake CDC Bridge
- 3-Stage Asynchronous Reset Synchronizer
- 4-Bit Bus Synchronizer (2-FF per bit)
- 4-Bit Gray Bus Synchronizer — L2 Upgrade
- Async Handshake Pulse Bridge
- Async Set Sync-Clear Flag — L2 Upgrade
- Asynchronous Reset Synchronizer for FIFO Gray Pointer Crossings
- Dual-Clock Pulse with Credit Return
- Enable Level Synchronizer — L1 Upgrade
- Four-Phase Req/Ack CDC Payload 16-bit
- Handshake CDC with 8-Bit Payload
- Multi-Bit Bus Synchronizer (2-FF)
- Multi-Bit Mux-Select Synchronizer — L2 Upgrade
- Pulse-Ack Round-Trip Across 2 Clocks
- Req/Ack Payload Hold 8-bit
- Single-Cycle Pulse Synchronizer (2-FF + Edge Detector)