Clock-Domain Crossing

Two-Stage Synchronizer Chain

Parameterized two-stage synchronizer for single-bit asynchronous signal crossing with optional async reset support.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Two-Stage Synchronizer Chain is a Verilog reference block in the Clock-Domain Crossing catalog. Clock-domain crossing FIFOs, synchronizers, and handshake bridges. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This OpenIP provides a two-stage synchronizer chain for safely crossing a single-bit asynchronous signal into a synchronous clock domain.

It mitigates metastability by sampling the asynchronous input twice on the destination clock edge, significantly improving mean time between failures (MTBF).

The module supports parameterizable reset polarity and optional asynchronous reset assertion.

Choose Open in IDE. RTL Studio loads the packaged workspace for Two-Stage Synchronizer Chain.
Read the Verilog module in the editor. The catalog line for this block: Parameterized two-stage synchronizer for single-bit asynchronous signal crossing with optional async reset support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Type	Description
`clk_sync`	input	wire	Destination (synchronizing) clock
`rst_sync_n`	input	wire	Synchronous active-low reset (ignored if `USE_ASYNC_RESET=1`)
`rst_async_n`	input	wire	Asynchronous active-low reset (used only if `USE_ASYNC_RESET=1`)
`data_in`	input	wire	Asynchronous input signal
`data_out`	output	wire	Synchronized output (alias of `data_out_sync`)
`data_out_sync`	output	wire	Double-synchronized output (primary use signal)

Verification

Test Case	Description	Pass Criteria
TC1	Power-on reset behavior	Outputs initialized to `RESET_POLARITY`
TC2	Single stable transition	Input change captured correctly after 2 cycles
TC3	Back-to-back toggles	No glitch propagation under worst-case timing
TC4	Random phase offset stress	All 10 random toggles synchronized correctly
TC5	Reset during transition	Reset overrides output without metastable latch
TC6	Continuous toggling (20 cycles)	Output tracks input with no errors

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