Counters
4-Digit BCD Up/Down Counter with Carry/Borrow
Synchronous 4-digit BCD counter with up/down control, load, and carry/borrow flags.
About this block
Simulate it in the Verilog IDE
4-Digit BCD Up/Down Counter with Carry/Borrow is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP core implements a synchronous 4-digit Binary Coded Decimal (BCD) counter. It supports both up-counting and down-counting operations, controlled by a direction signal. The module includes synchronous load functionality for preset values and asserts carry/borrow flags when wrapping from 9999 to 0000 or vice versa. Designed for standard ASIC and FPGA synthesis flows, this counter is ideal for digital displays, timers, and BCD-based arithmetic logic units.
This 4-digit BCD counter provides a robust solution for decimal counting applications. It handles carry and borrow propagation correctly across all digit boundaries. The synchronous load and enable features offer flexible integration into larger systems. Use this IP for digital displays, timers, or any BCD-based arithmetic logic.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Digit BCD Up/Down Counter with Carry/Borrow.
- Read the Verilog module in the editor. The catalog line for this block: Synchronous 4-digit BCD counter with up/down control, load, and carry/borrow flags.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- 4-Digit BCD Counting: Counts from 0000 to 9999.
- Up/Down Control: Direction controlled via a single input signal.
- Synchronous Load: Load a preset value synchronously with the clock.
- Carry/Borrow Flags: Asserts flags on overflow (9999 -> 0000) and underflow (0000 -> 9999).
- Asynchronous Reset: Active-low reset for immediate initialization.
- Synthesizable: Verified for standard ASIC and FPGA tools.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
clk | Input | 1 | System clock signal |
rst_n | Input | 1 | Active-low asynchronous reset |
load | Input | 1 | Synchronous load enable |
dir | Input | 1 | Count direction (0=Up, 1=Down) |
data_in | Input | 16 | Preset value for synchronous load |
count_out | Output | 16 | Current counter value |
carry | Output | 1 | Carry flag for up-count overflow |
borrow | Output | 1 | Borrow flag for down-count underflow |
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