Counters

Dual Compare-Match Counter 8 — L1 Upgrade — L2 Upgrade

An 8-bit counter with dual compare-match outputs and an interrupt request signal.

Open in IDE Category Wiki · counters

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

Dual Compare-Match Counter 8 — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

An 8-bit dual compare-match counter with parallel load, enable control, and interrupt request generation. This IP is designed for precise timing control and event detection in digital systems.

This IP provides a robust 8-bit counter with dual match capabilities.

It supports synchronous reset, parallel load, and count enable functionality.

Choose Open in IDE. RTL Studio loads the packaged workspace for Dual Compare-Match Counter 8 — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit counter with dual compare-match outputs and an interrupt request signal.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Counter: Counts from 0 to 255.
Dual Compare-Match: Two independent 8-bit match thresholds (match_value_a, match_value_b).
Interrupt Generation: match_irq asserts high when the counter matches either threshold.
Parallel Load: Load a specific value into the counter via load_value.
Synchronous Reset: Resets counter to 0 on active-low rst_n.
Count Enable: Increment counter only when en is high.

Architecture

The module consists of an 8-bit counter register and two comparators. A synchronous load path allows overwriting the counter with a parallel value. An enable signal controls whether the counter increments on the rising clock edge. Reset logic forces the counter to zero when the active-low reset signal is asserted.

### Logic Priority

Reset (rst_n == 0): Counter resets to 0.
Load (load == 1): Counter loads load_value.
Enable (en == 1): Counter increments.
Idle: Counter holds current value.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low synchronous reset
en	Input	1	Count enable
load	Input	1	Parallel load enable
load_value	Input	8	Value to load into counter
match_value_a	Input	8	First match threshold
match_value_b	Input	8	Second match threshold
count	Output	8	Current counter value
match_a	Output	1	High when count equals match_value_a
match_b	Output	1	High when count equals match_value_b
match_irq	Output	1	High when count equals either match value

Verification

The testbench verifies reset, load, enable, and match behaviors. All six test cases passed successfully in simulation.

Test Case	Description	Result
TC1	Reset behavior	PASS
TC2	Load value	PASS
TC3	Count enable	PASS
TC4	Match A	PASS
TC5	Match B	PASS
TC6	No match	PASS

More in Counters

All Counters blocks