Counters

4-Bit Down Counter

Synchronous 4-bit down counter with asynchronous reset, parallel load, and enable control.

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About this block

Simulate it in the Verilog IDE

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4-Bit Down Counter is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

A synchronous 4-bit down counter with asynchronous reset, parallel load, and enable control.

This module implements a 4-bit down counter in Verilog. It supports asynchronous active-low reset. It supports synchronous parallel load via the load signal. It supports counting down when the en signal is asserted. The load signal has priority over the en signal.

This 4-bit down counter provides a simple and reliable counting solution. It supports asynchronous reset for immediate initialization. It supports synchronous parallel load for flexible data injection. It supports count enable for power-saving or conditional counting. The load signal takes precedence over the enable signal. The design wraps around from 0 to 15 automatically.

Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Bit Down Counter.
Read the Verilog module in the editor. The catalog line for this block: Synchronous 4-bit down counter with asynchronous reset, parallel load, and enable control.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The following block diagram illustrates the signal flow.

Interface

The module exposes the following ports.

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Asynchronous active-low reset
`load`	Input	1	Synchronous parallel load enable
`en`	Input	1	Count enable
`din`	Input	4	Parallel data input
`q`	Output	4	Counter output

Verification

The design was verified using Icarus Verilog. The testbench covers reset, load, count down, load priority, and wrap-around behavior.

Test Case	Description	Result
TC1	Asynchronous reset to zero	PASS
TC2	Synchronous parallel load	PASS
TC3	Count down operation	PASS
TC4	Load priority over enable	PASS
TC5	Wrap-around from 0 to 15	PASS

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