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Bidirectional Counter 4-Bit — L1 Upgrade — L2 Upgrade

Bidirectional Counter 4-Bit with load enable and match interrupt generation.

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About this block

Simulate it in the Verilog IDE

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Bidirectional Counter 4-Bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a 4-bit bidirectional counter with synchronous load, direction control, and a match-based interrupt generation feature. It is designed for applications requiring precise counting, event detection, and interrupt-driven control logic.

The design is fully verified with Icarus Verilog and ready for integration into larger systems.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Bidirectional Counter 4-Bit — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Bidirectional Counter 4-Bit with load enable and match interrupt generation.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • 4-Bit Bidirectional Counting: Counts up or down based on the up_dn control signal.
  • Synchronous Parallel Load: Loads a 4-bit value from load_value when load_en is high.
  • Match Interrupt: Generates an interrupt request (irq) when count == match_value and match_en is high.
  • Synchronous Active-Low Reset: Resets the counter and interrupt to zero on the active edge of rst_n.
  • Verified Design: All functional scenarios verified via Icarus Verilog simulation.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low synchronous reset
load_enInput1Parallel load enable
up_dnInput1Direction control (1=Up, 0=Down)
load_valueInput4Parallel load data input
match_valueInput4Match comparison value
match_enInput1Match interrupt enable
irqOutput1Interrupt request signal
countOutput4Counter output value

Verification

The testbench (tb_bidirectional_counter_load_enable_4bit_match_irq_load.v) verifies the following scenarios:

  • TC1: Reset: Verifies that count and irq are initialized to 0 when rst_n is low.
  • TC2: Load: Verifies that count updates to load_value when load_en is high.
  • TC3: Up Count: Verifies that count increments when up_dn is high and load_en is low.
  • TC4: Down Count: Verifies that count decrements when up_dn is low and load_en is low.
  • TC5: Match IRQ: Verifies that irq asserts high when count == match_value and match_en is high.
  • TC6: No Match IRQ: Verifies that irq deasserts when count != match_value.

All test cases passed successfully.

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