Counters

8-Bit Up/Down Counter

An 8-bit up/down counter with synchronous load and asynchronous reset.

Open in IDE Category Wiki · counters

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

8-Bit Up/Down Counter is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

A robust 8-bit up/down counter module with synchronous load and asynchronous reset capabilities. Designed for flexible integration into digital systems requiring precise counting control.

This module implements an 8-bit up/down counter that supports:

Asynchronous Active-Low Reset: Resets output to zero immediately.
Synchronous Load: Loads a specific value on the next clock edge.
Up/Down Counting: Increments or decrements based on direction control.
Enable Control: Disables counting when disabled.

Simulation results confirm correct operation across all modes, including reset, load, up/down counting, and wrap-around behavior.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Up/Down Counter.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit up/down counter with synchronous load and asynchronous reset.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Output: Provides an 8-bit output register q.
Synchronous Load: Supports loading a specific value via load and load_val inputs.
Direction Control: Controlled by the dir input signal (1 for up, 0 for down).
Enable Control: Managed by the en input signal to enable/disable counting.
Asynchronous Reset: Resets to zero on a low pulse of the rst_n signal, regardless of the clock.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Asynchronous reset, active low
en	Input	1	Enable counter operation
dir	Input	1	Direction: 1 for up, 0 for down
load_val	Input	[7:0]	Value to load into counter
load	Input	1	Load enable signal
q	Output	[7:0]	Counter output

Architecture

The following diagram illustrates the data flow and control logic.

Verification

The testbench verifies reset, load, up counting, down counting, and wrap-around behavior. All six test cases passed successfully in the simulation log.

Test Case	Description	Result
TC1	Reset Test	PASS
TC2	Load Value Test	PASS
TC3	Up Counting Test	PASS
TC4	Down Counting Test	PASS
TC5	Wrap-around Test (Up)	PASS
TC6	Wrap-around Test (Down)	PASS

More in Counters

All Counters blocks