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Counters

4-Bit Counter with Wrap Strobe

A 4-bit free-running counter with synchronous enable, load, and a wrap strobe output that pulses when the count rolls over from 15 to 0.

Open in IDE Category Wiki · counters

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

4-Bit Counter with Wrap Strobe is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a 4-bit free-running counter with enable and synchronous load capabilities.

It generates a single-cycle pulse (wrap_stb) when the counter wraps from 15 to 0.

The module is suitable for basic timing, event counting, or sequence generation tasks.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Bit Counter with Wrap Strobe.
  2. Read the Verilog module in the editor. The catalog line for this block: A 4-bit free-running counter with synchronous enable, load, and a wrap strobe output that pulses when the count rolls over from 15 to 0.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • 4-bit counting range: Counts from 0 to 15.
  • Synchronous Enable: Counting occurs only when en is high.
  • Synchronous Load: Arbitrary initial values can be loaded via load_val when load_en is high.
  • Wrap Strobe: Active-high pulse generated when the counter reaches 15 (gated by en).
  • Asynchronous Reset: Active-low rst_n resets the counter to 0 immediately.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Asynchronous active-low reset
enInput1Synchronous enable
load_valInput4Load data input
load_enInput1Synchronous load enable
doutOutput4Counter output
wrap_stbOutput1Wrap strobe pulse

Verification

The design includes a comprehensive testbench (tb_wrap_strobe_4bit.v) that verifies all functional modes. Simulation was performed using Icarus Verilog. All five test cases passed successfully.

Test CaseDescriptionResult
TC1Reset to 0PASS
TC2Count 0->15->0 with enablePASS
TC3Wrap strobe high at 15PASS
TC4Value unchanged while en=0PASS
TC5Synchronous load worksPASS

Integration

To integrate this IP into your project:

  1. Copy rtl/wrap_strobe_4bit.v to your RTL directory.
  2. Instantiate the module in your top-level design.
  3. Ensure clk is driven by your system clock.
  4. Handle rst_n according to your system reset strategy.

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