Counters

16-Bit Cycle Counter with Prescaler — L1 Upgrade — L2 Upgrade

16-bit cycle counter with prescaler, load enable, match interrupt, and synchronous reset.

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16-Bit Cycle Counter with Prescaler — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a configurable 16-bit cycle counter with prescaler support, load enable, match interrupt generation, and synchronous reset. It is designed for timing control and event counting applications in FPGA and ASIC designs.

The design is fully verified with Icarus Verilog and includes a comprehensive testbench.

This IP provides a configurable 16-bit counter capable of prescaling the input clock frequency. Key features include:

Prescaler Support: Divides the input clock frequency by 2 when enabled.
Load Enable: Allows immediate loading of a 16-bit value into the counter.
Match Interrupt: Asserts an interrupt request (IRQ) when the counter value matches a target match_value.
Synchronous Reset: Resets the counter and prescaler to zero on the active-low reset signal.

Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Bit Cycle Counter with Prescaler — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 16-bit cycle counter with prescaler, load enable, match interrupt, and synchronous reset.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design consists of two main stages:

Prescaler Stage: A toggle flip-flop that divides the clock frequency by 2 when prescale_en is high.
Counter Stage: A 16-bit counter that increments on the rising edge of the clock if the prescaler state is high. It supports immediate loading via load_en and generates an IRQ when count == match_value.

### Logic Flow

Reset: rst_n low resets count and irq to 0, and prescale_state to 0.
Prescaler: Toggles prescale_state on every clock edge if prescale_en is high.
Counter Update:

- If load_en is high, count loads load_value. - Else if prescale_state is high, count increments by 1.

IRQ Generation: irq is asserted high if count equals match_value, otherwise it is deasserted.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`load_en`	Input	1	Load enable signal
`prescale_en`	Input	1	Prescaler enable signal
`load_value`	Input	16	Value to load into counter
`match_value`	Input	16	Value to match for IRQ assertion
`irq`	Output	1	Interrupt request signal
`count`	Output	16	Current counter value

Verification

The testbench verifies the following functionalities:

TC1: Checks that count and irq are zero after reset.
TC2: Verifies that load_en correctly loads load_value into count.
TC3: Confirms that the counter increments when prescale_en is active.
TC4: Asserts that irq goes high when count matches match_value.
TC5: Ensures that irq goes low when the match condition is cleared.

All five test cases passed successfully in simulation.

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