Counters

8-Bit Johnson Counter (Twisted Ring) — L1 Upgrade — L2 Upgrade

8-Bit Johnson Counter with parallel load, count enable, and match-based interrupt generation.

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8-Bit Johnson Counter (Twisted Ring) — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements an 8-bit Johnson Counter (also known as a Twisted Ring Counter). It supports parallel loading, synchronous counting, and a match-based interrupt generation mechanism. The feedback path inverts the least significant bit (LSB) and feeds it back to the most significant bit (MSB), creating a sequence of 16 unique states.

The match interrupt is registered to prevent combinational glitches, ensuring stable output in synchronous systems.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Johnson Counter (Twisted Ring) — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-Bit Johnson Counter with parallel load, count enable, and match-based interrupt generation.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Johnson Counter Sequence: Generates a 16-state twisted ring pattern.
Synchronous Load: Parallel data input via load_value when load_en is asserted.
Synchronous Count Enable: State progression controlled by count_en.
Match Comparator: Compares current state q with match_value.
Registered Interrupt: match_irq is registered to ensure glitch-free output.
Asynchronous Reset: Active-low reset via rst_n.
Verified: Fully verified with Icarus Verilog simulation.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`load_en`	Input	1	Synchronous load enable
`count_en`	Input	1	Synchronous count enable
`load_value`	Input	8	Parallel load data
`match_value`	Input	8	Comparator match value
`match_irq`	Output	1	Match interrupt flag (registered)
`q`	Output	8	Counter output

Verification

The testbench verifies the following functionalities:

Reset: Ensures q and match_irq are zero after reset.
Load: Verifies parallel loading of load_value.
Counting: Checks the full 16-state Johnson sequence.
Match IRQ: Verifies assertion and de-assertion of match_irq when q == match_value.

Test Case	Description	Result
TC1	Reset state and IRQ check	PASS
TC2	Parallel load check	PASS
TC3	Johnson sequence check (16 steps)	PASS
TC4	Match IRQ check	PASS

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