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8-Bit Ring Counter

An 8-bit ring counter with synchronous load and circular right shift functionality.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

8-Bit Ring Counter is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit ring counter with synchronous load and reset capabilities. It shifts data right in a circular fashion when the load enable is disabled, feeding the least significant bit (LSB) back into the most significant bit (MSB). A synchronous active-low reset initializes the counter to a predefined seed value (8'b00000001). This IP is suitable for sequence detection, pattern generation, and control applications requiring deterministic state progression.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Ring Counter.
  2. Read the Verilog module in the editor. The catalog line for this block: An 8-bit ring counter with synchronous load and circular right shift functionality.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • 8-bit Width: Supports 8-bit data paths.
  • Synchronous Load: Allows external data injection via data_in when load_en is asserted.
  • Circular Shift: Automatically shifts right, wrapping the LSB to the MSB.
  • Synchronous Reset: Resets to a predefined seed (00000001) on the rising clock edge.
  • Deterministic State: Ensures predictable behavior for control logic applications.

Architecture

The core component is an 8-bit register. The feedback path connects the LSB (state[0]) to the MSB (state[7]) during shift operations. The control logic prioritizes reset, then load, then shift.

### Data Flow

  1. Reset: If rst_n is low, state becomes 8'b00000001.
  2. Load: If rst_n is high and load_en is high, state becomes data_in.
  3. Shift: If neither reset nor load is active, state shifts right: {state[0], state[7:1]}.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input signal
rst_nInput1Active-low synchronous reset
load_enInput1Load enable signal
data_inInput8Data input for loading
qOutput8Counter output state

Verification

The provided testbench (tb_ring_counter_8b) validates the following scenarios:

  • TC1: Reset value check (verifies initial state is 00000001).
  • TC2: Load functionality check (verifies data_in is correctly loaded).
  • TC3: Circulation sequence check (verifies bit rotation).
  • TC4: Reset during operation check (verifies reset overrides shift/load).
  • TC5: Load different pattern check (verifies arbitrary pattern loading).

### Running the Testbench

  1. Ensure you have a Verilog simulator installed (e.g., Icarus Verilog, ModelSim).
  2. Navigate to the simulation directory.
  3. Run the simulation:
  4. Check the console output for PASS/FAIL results and generate VCD for waveform analysis.

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