Counters

Event Counter with Capture

16-bit event counter with rising-edge detection and synchronous capture register.

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About this block

Simulate it in the Verilog IDE

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Event Counter with Capture is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 16-bit event counter with rising-edge detection and snapshot capture capability. It detects rising edges on the event_in signal and increments an internal counter. A capture register allows snapshotting the current count value on demand. The design supports asynchronous reset and synchronous clear operations.

This IP provides a robust solution for counting events with the ability to snapshot the count at specific moments. It is suitable for applications requiring event tracking and periodic data logging. The design is simple, efficient, and fully verified.

Choose Open in IDE. RTL Studio loads the packaged workspace for Event Counter with Capture.
Read the Verilog module in the editor. The catalog line for this block: 16-bit event counter with rising-edge detection and synchronous capture register.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

16-bit counting range (0 to 65535).
Rising-edge detection for debounced or pulse-based event inputs.
Synchronous capture of the current count value.
Synchronous clear to zero the counter.
Asynchronous active-low reset for system initialization.
Fully synchronous design suitable for high-frequency synthesis.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input for synchronous logic.
`rst_n`	Input	1	Asynchronous active-low reset.
`event_in`	Input	1	Event signal to count rising edges.
`cap_en`	Input	1	Capture enable to snapshot `count_out`.
`clr`	Input	1	Synchronous clear to reset counter to zero.
`count_out`	Output	16	Current count value.
`cap_out`	Output	16	Captured count value snapshot.

Architecture

The module consists of two main stages: edge detection and counting, followed by capture logic. The edge detector uses a two-stage flip-flop chain to identify rising edges on event_in. A pulse is generated when the previous state was low and the current state is high. The counter increments on each detected pulse unless cleared or reset. The capture register samples the counter value when cap_en is asserted.

Verification

The testbench verifies reset behavior, counting accuracy, capture functionality, and clear operation. All test cases passed successfully during simulation.

Test Case	Description	Result
TC1	Reset behavior	PASS
TC2	Count rising edges	PASS
TC3	Capture value	PASS
TC4	Continue counting after capture	PASS
TC5	Clear counter	PASS

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