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4-Bit Counter Match Pulse

4-Bit Counter Match Pulse

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About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

4-Bit Counter Match Pulse is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This Intellectual Property (IP) implements a 4-bit up-counter with a configurable match detection feature. It generates a single-cycle pulse (match_stb) when the counter value equals a target value (match). Upon matching, the counter automatically resets to zero, making it ideal for periodic event generation, timeout counters, and sequence detection.

This IP provides a robust, synchronous 4-bit counter with match detection capabilities.

It is designed for simplicity and ease of integration, featuring a clear interface and comprehensive verification.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 4-Bit Counter Match Pulse.
  2. Read the Verilog module in the editor. The catalog line for this block: 4-Bit Counter Match Pulse.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • 4-Bit Up-Counter: Counts from 0 to 15.
  • Configurable Match: Target value set via the match input port.
  • Synchronous Reset: Active-low reset (rst_n) clears the counter state.
  • Enable Control: en signal allows pausing/resuming the count.
  • Match Pulse: match_stb asserts for exactly one clock cycle when dout == match.
  • Auto-Reset: Counter resets to 0 immediately after a match is detected.

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