Counters

8-Bit Leading Zero Counter — L1 Upgrade — L2 Upgrade

An 8-bit leading zero counter with synchronous load, enable, and match interrupt generation.

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8-Bit Leading Zero Counter — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements an 8-bit leading zero counter with synchronous load and match interrupt capabilities. It calculates the number of leading zeros in an 8-bit input vector and asserts an interrupt (irq_match) when the count matches a configurable threshold.

Designed for L1/L2 cache line processing or bit-slice operations, it features a fully verified RTL implementation using standard synchronous logic patterns.

The module provides a combinational leading zero detection mechanism registered on the positive clock edge. It supports:

Load: Preset the output count directly from an input value.
Enable: Process data_in to calculate leading zeros.
Match Interrupt: Assert irq_match when count_out equals match_value.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Leading Zero Counter — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit leading zero counter with synchronous load, enable, and match interrupt generation.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Width: 8-bit data input and output.
Logic: Combinational case-statement based leading zero detection.
Control: Synchronous load and enable signals.
Reset: Asynchronous active-low reset (rst_n).
Interrupt: Configurable match interrupt via match_value.
Verification: Verified with Icarus Verilog simulation covering load, enable, and edge cases.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Asynchronous active-low reset
`load`	Input	1	Load enable signal (overrides enable)
`enable`	Input	1	Data processing enable signal
`data_in`	Input	[7:0]	Input data vector
`load_value`	Input	[7:0]	Value to load into `count_out`
`match_value`	Input	[7:0]	Threshold for interrupt match
`count_out`	Output	[7:0]	Calculated leading zero count
`irq_match`	Output	1	Interrupt signal when `count_out == match_value`

Architecture

The design uses a single synchronous always block triggered by posedge clk or negedge rst_n.

Reset: count_out and irq_match are cleared to zero.
Load Priority: If load is asserted, count_out takes load_value.
Enable: If enable is asserted (and load is deasserted), count_out is calculated from data_in.
Interrupt: irq_match is registered high if count_out == match_value.

Verification

The IP is verified using a testbench that covers:

Load Functionality: Verifying preset values (e.g., 8, 0, 7).
Enable Functionality: Verifying leading zero counts for specific inputs (0x00, 0x80, 0x40, 0x20).
Match Logic: Verifying irq_match assertion/deassertion based on match_value.

### Test Case Summary

TC	Input/Action	Expected `count_out`	Expected `irq_match`
1	Load 8	8	1 (if match=8)
2	Load 0	0	1 (if match=0)
3	Enable 0x00	8	1 (if match=8)
4	Enable 0x80	0	1 (if match=0)
5	Enable 0x40	1	1 (if match=1)
6	Enable 0x20	2	0 (if match!=2)

All test cases passed in Icarus Verilog simulation.

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