Counters

Gray-Code Counter 8-Bit — L2 Upgrade

An 8-bit binary counter with pipelined Gray-code conversion, supporting load, enable, and backpressure.

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About this block

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Gray-Code Counter 8-Bit — L2 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This Intellectual Property (IP) implements an 8-bit binary counter with pipelined Gray-code conversion. It is designed for applications requiring single-bit transitions in the output domain, such as asynchronous clock domain crossings (CDC) or low-power designs where glitch minimization is critical.

The module supports synchronous load, enable control, and ready-based backpressure to integrate seamlessly into larger data paths.

This IP provides a robust 8-bit Gray-code counter with pipelined outputs. It supports standard control interfaces for integration into larger systems. Verification confirms functional correctness across all control modes.

Choose Open in IDE. RTL Studio loads the packaged workspace for Gray-Code Counter 8-Bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit binary counter with pipelined Gray-code conversion, supporting load, enable, and backpressure.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Binary Counting: Supports overflow wrap-around from 0xFF to 0x00.
Gray-Code Conversion: Combinatorial generation of Gray code from internal binary state.
Pipelined Outputs: Registers stabilize outputs to improve timing closure in high-frequency designs.
Synchronous Load: Allows injection of an initial value via bin_in.
Backpressure Handling: ready signal halts counting when asserted low.
Valid Flag: Indicates when bin_out and gray_out contain valid data.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input (positive edge triggered)
rst_n	Input	1	Active-low asynchronous reset
load	Input	1	Synchronous load enable
en	Input	1	Count enable
bin_in	Input	8	Binary input for load
ready	Input	1	Backpressure ready signal (high = count allowed)
bin_out	Output	8	Current binary count
gray_out	Output	8	Current Gray-code count
valid	Output	1	Output valid flag (high when counting or loaded)

Architecture

The module consists of two main stages:

Binary Counter: Updates on the clock edge when en and ready are high, or when load is high.
Gray-Code Converter: Generates Gray code from the internal binary state using XOR operations.

### Data Flow

*Note: The valid signal is asserted high when the counter is actively counting (en && ready) or when a load operation is performed. It is deasserted otherwise.*

Verification

The testbench covers reset, counting, backpressure, load, and disable scenarios. Simulation results confirm correct Gray-code sequence generation.

Test Case	Description	Result
TC1	Reset check	PASS
TC2	Counting and Gray conversion	PASS
TC3	Backpressure hold	PASS
TC4	Load functionality	PASS
TC5	Disable check	PASS

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