Counters

Loadable Down Counter 8-Bit — L1 Upgrade — L2 Upgrade

Fully synthesizable 8-bit loadable down counter with match and zero interrupt requests.

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About this block

Simulate it in the Verilog IDE

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Loadable Down Counter 8-Bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a fully synthesizable, latch-free 8-bit loadable down counter. It supports asynchronous active-low reset, independent load and count enable controls, and generates interrupt requests (irq_match and irq_zero) based on counter state. The design is compliant with Verilog-2001 standards and includes a comprehensive testbench for verification.

Key Features:

8-bit Counting: Counts down from a loaded value to zero.
Control Signals: Independent load_en and count_en inputs.
Interrupts: Asserts irq_match when counter equals match_value; asserts irq_zero when counter reaches zero.
Reset: Asynchronous active-low reset (rst_n).
Verification: Includes a testbench with 7 test cases covering reset, load, count, match, and zero behaviors.

Choose Open in IDE. RTL Studio loads the packaged workspace for Loadable Down Counter 8-Bit — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Fully synthesizable 8-bit loadable down counter with match and zero interrupt requests.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset input
`load_en`	Input	1	Load enable input (Priority over count_en)
`count_en`	Input	1	Count enable input
`load_value`	Input	8	Data value to load into counter
`match_value`	Input	8	Value to match against for `irq_match`
`irq_match`	Output	1	Match interrupt output (Combinational)
`irq_zero`	Output	1	Zero interrupt output (Combinational)
`counter_out`	Output	8	Current counter value

Architecture

The internal signal flow is illustrated below:

Verification

The provided testbench (tb/tb_loadable_down_irq_8_match_irq_load.v) verifies the following behaviors:

Test Case	Description	Result
TC1	Reset behavior	PASS
TC2	Load value	PASS
TC3	Count down and match IRQ	PASS
TC4	Count to zero and zero IRQ	PASS
TC5	Reload and verify match IRQ	PASS
TC6	IRQ match deassertion	PASS
TC7	IRQ zero deassertion	PASS

Running Simulation: After running the simulation, the Log panel should display:

TC1 PASS reset
TC2 PASS load
TC3 PASS count down and match
TC4 PASS count to zero
TC5 PASS reload
TC5 PASS reload and match
TC6 PASS IRQ deassert
TC7 PASS IRQ zero deassert

Use the RtlStudio Waveform tab with sim/dump.vcd for visual inspection of signals.

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