Counters

Decade BCD Counter 1-Digit — L1 Upgrade

A 1-digit Decade BCD counter with synchronous load, enable, and asynchronous reset.

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About this block

Simulate it in the Verilog IDE

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Decade BCD Counter 1-Digit — L1 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a 1-digit Decade BCD (Binary-Coded Decimal) counter.

It counts from 0 to 9 and wraps around to 0 on the next clock cycle.

The design supports asynchronous active-low reset, synchronous load of a 4-bit input value, and synchronous enable to hold the current count.

Choose Open in IDE. RTL Studio loads the packaged workspace for Decade BCD Counter 1-Digit — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 1-digit Decade BCD counter with synchronous load, enable, and asynchronous reset.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Counts 0-9 in BCD format.
Synchronous load input for presetting the counter.
Synchronous enable input to pause counting.
Asynchronous active-low reset to clear the output.
Simple 4-bit data path.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Asynchronous reset, active low
`load`	Input	1	Synchronous load enable
`enable`	Input	1	Synchronous count enable
`d_in`	Input	4	Data input for load operation
`q_out`	Output	4	Counter output

Verification

The testbench verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Reset	`q_out` becomes 0
TC2	Load	`q_out` takes `d_in` value
TC3	Count Up	`q_out` increments to 9
TC4	Wrap	`q_out` wraps from 9 to 0
TC5	Disable	`q_out` holds value when `enable` is low
TC6	Load Different	`q_out` updates with new `d_in`

All test cases passed successfully. After Run Simulation, the Log panel should show:

TC1 PASS Reset
TC2 PASS Load
TC3 PASS Count to 9
TC4 PASS Wrap
TC5 PASS Disable
TC6 PASS Load different
Simulation ends with INFO: PASS.

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