Counters

Loadable 4-Bit Up Counter

A fully synthesizable 4-bit up counter with synchronous load, enable, and asynchronous reset capabilities.

Open in IDE Category Wiki · counters

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

Loadable 4-Bit Up Counter is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a fully synthesizable 4-bit up counter with synchronous load and enable controls. It is designed for reliable integration into FPGA and ASIC designs, adhering to Verilog-2001 standards.

The counter supports asynchronous reset, synchronous loading of a 4-bit data word, and automatic wrap-around from 15 (0xF) to 0. All logic is registered, ensuring clean timing closure.

Choose Open in IDE. RTL Studio loads the packaged workspace for Loadable 4-Bit Up Counter.
Read the Verilog module in the editor. The catalog line for this block: A fully synthesizable 4-bit up counter with synchronous load, enable, and asynchronous reset capabilities.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

4-Bit Width: Counts from 0 to 15.
Synchronous Load: Updates the counter value synchronously when the load signal is asserted.
Synchronous Enable: Holds the current state when en is deasserted.
Asynchronous Reset: Clears the output to zero immediately when rst_n is low.
Wrap-Around: Automatically resets to 0 after reaching 15.
Latch-Free: Ensures predictable synthesis results.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input for synchronous operations.
rst_n	Input	1	Asynchronous active-low reset signal.
load	Input	1	Synchronous load control signal.
en	Input	1	Synchronous enable signal for counting.
d	Input	4	Data input for loading into the counter.
q	Output	4	Current counter value output.

Verification

The testbench covers reset behavior, counting with enable, synchronous loading, and wrap-around logic. All test cases passed successfully in the Icarus Verilog simulation environment.

### Running Simulation

### Expected Results

After running the simulation, the Log panel should show:

TC1 PASS: Reset cleared output to 0
TC2 Step 1 PASS: Counted to 1
TC2 Step 2 PASS: Counted to 2
TC2 Step 3 PASS: Held value at 2
TC2 Step 4 PASS: Resumed counting to 3
TC3 PASS: Loaded value A
TC4 Pre-wrap PASS: Reached 15
TC4 PASS: Wrapped to 0

Test Case	Description	Result
TC1	Reset Test	PASS
TC2	Counting with Enable	PASS
TC3	Synchronous Load	PASS
TC4	Wrap-around	PASS

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