Counters

8-Bit Binary Up Counter — L1 Upgrade — L2 Upgrade

8-Bit Binary Up Counter with load enable and match interrupt request generation.

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About this block

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8-Bit Binary Up Counter — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements an 8-bit binary up-counter with synchronous load, enable control, and a match-based interrupt request (IRQ) signal. It is designed for applications requiring precise timing, event counting, or periodic interrupt generation in digital systems.

This 8-bit binary up counter provides a robust, verified solution for counting and interrupt generation.

It supports flexible control via synchronous load and enable signals, making it suitable for applications requiring precise timing and event detection.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Binary Up Counter — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-Bit Binary Up Counter with load enable and match interrupt request generation.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-Bit Counting: Counts from 0x00 to 0xFF.
Synchronous Load: Allows presetting the counter value via load_value when load is asserted.
Enable Control: Counting occurs only when en is high.
Match IRQ: Asserts irq high when count equals match_value.
Asynchronous Reset: Active-low rst_n resets the counter to 0 immediately.
Verified: Fully verified with Icarus Verilog simulation.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`en`	Input	1	Count enable (high = count)
`load`	Input	1	Load control (high = load `load_value`)
`load_value`	Input	8	Data to load into counter
`match_value`	Input	8	Threshold value for IRQ assertion
`count`	Output	8	Current counter value
`irq`	Output	1	Interrupt request (high when `count == match_value`)

Verification

The provided testbench (tb/tb_binary_up_counter_load_enable_8bit_match_irq_load.v) verifies the following behaviors:

Test Case	Description	Result
TC1	Reset behavior	PASS
TC2	Count enable and freeze	PASS
TC3	Load functionality	PASS
TC4	Match IRQ assertion	PASS
TC5	IRQ deassertion after match	PASS

### Running the Simulation

To run the simulation:

### Expected Output

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