RTL Studio Open IDE

Counters

Modulo-N Counter

A parameterized modulo-N counter with asynchronous reset and terminal count output.

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

Modulo-N Counter is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

A parameterized modulo-N counter with asynchronous reset and terminal count output.

This IP implements a configurable up-counter that wraps at a specified modulus N.

It is resource-efficient, using automatic width calculation to minimize logic usage.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Modulo-N Counter.
  2. Read the Verilog module in the editor. The catalog line for this block: A parameterized modulo-N counter with asynchronous reset and terminal count output.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Parameterizable Modulus: Set the modulus N via a parameter.
  • Resource Efficient: Automatic width calculation using $clog2 ensures only necessary bits are used.
  • Control Signals: Supports synchronous enable and asynchronous active-low reset.
  • Terminal Count: Generates a pulse (tc) when the counter reaches N-1.
  • Standard Interface: 8-bit output count (zero-padded) for compatibility.

Architecture

The internal counter uses the minimum bits required to represent N states. The terminal count logic compares the internal counter against N-1. On reaching N-1, the next enable pulse resets the counter to zero. An asynchronous reset forces the counter to zero immediately.

The output count is assigned from the internal register, zero-padded to 8 bits.

Ports

PortDirectionWidthDescription
clkInput1Clock input
rst_nInput1Asynchronous active-low reset
enInput1Synchronous enable
countOutput8Counter value (zero-padded)
tcOutput1Terminal count pulse

Parameters

ParameterDefaultDescription
N10Modulus of the counter

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