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Parameterized N-Bit Counter with Enable and Wrap — L1 Upgrade — L2 Upgrade

Parameterized N-Bit Counter with Enable, Wrap, Load, Match IRQ

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About this block

Simulate it in the Verilog IDE

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Parameterized N-Bit Counter with Enable and Wrap — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a parameterized N-bit counter with enable, wrap, load, match, and IRQ capabilities.

The design is fully synthesizable Verilog-2001 code with no latch-free dependencies.

It supports asynchronous reset and synchronous load operations.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Parameterized N-Bit Counter with Enable and Wrap — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Parameterized N-Bit Counter with Enable, Wrap, Load, Match IRQ.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Configurable bit-width: Default 8-bit, easily parameterized.
  • Synchronous Enable: Counting occurs only when en is high.
  • Synchronous Load: Load load_value into the counter when load is high.
  • Automatic Wrap-Around: Counter resets to zero upon reaching maximum value.
  • Match Detection: Configurable match value for event detection.
  • Interrupt Request (IRQ): Asserted when count == match_value and match_en is high.
  • Asynchronous Reset: Active-low rst_n resets counter and IRQ to zero.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Asynchronous active-low reset
enInput1Count enable
loadInput1Load control
match_enInput1Match enable
load_valueInput[N-1:0]Value to load into counter
match_valueInput[N-1:0]Value to match against
countOutput[N-1:0]Current counter value
irqOutput1Interrupt request signal

*Note: N is the parameterized bit-width (default 8).*

Verification

The testbench verifies:

  • Reset behavior (count and IRQ go to zero).
  • Counting up when en is high.
  • Loading load_value when load is high.
  • IRQ assertion when count == match_value and match_en is high.
  • Wrap-around from max value to zero.
  • IRQ deassertion when match condition is no longer met.

### Running Simulation

  1. Ensure Icarus Verilog is installed.
  2. Run the simulation script or command:
  3. Check the Log panel for the following expected results:

- TC1 PASS reset count - TC1 PASS reset irq - TC2 PASS count up - TC3 PASS load value - TC4 PASS irq asserted at match - TC5 PASS wrap - TC6 PASS irq deasserted - Simulation ends with INFO: PASS.

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