Counters
Sticky Overflow Counter 8-bit — L1 Upgrade — L2 Upgrade
An 8-bit counter with load enable, match-based IRQ, and sticky overflow detection for L1/L2 upgrades.
About this block
Simulate it in the Verilog IDE
Sticky Overflow Counter 8-bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Counters catalog. Up/down, modulo, and loadable binary counters with enable logic. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP implements an 8-bit counter with load enable, match-based IRQ, and sticky overflow detection. It is designed for L1 and L2 upgrade scenarios requiring precise event counting and status tracking. The module supports synchronous reset, parallel load, and continuous counting modes.
This IP provides a robust 8-bit counting solution with advanced status flags for system monitoring. It integrates seamlessly into L1 and L2 upgrade paths for legacy counter replacements. The design is fully verified and ready for synthesis and integration.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Sticky Overflow Counter 8-bit — L1 Upgrade — L2 Upgrade.
- Read the Verilog module in the editor. The catalog line for this block: An 8-bit counter with load enable, match-based IRQ, and sticky overflow detection for L1/L2 upgrades.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
The counter increments on every active clock edge when count enable is asserted. A parallel load operation overrides the count function when load enable is high. The sticky overflow flag remains set once the counter wraps from 0xFF to 0x00. An IRQ match signal asserts when the counter value equals the configured match value. Loading a new value clears both the sticky overflow and IRQ match flags.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock input |
| rst_n | Input | 1 | Active-low synchronous reset |
| load_en | Input | 1 | Load enable signal |
| count_en | Input | 1 | Count enable signal |
| load_value | Input | 8 | Parallel load data input |
| match_value | Input | 8 | IRQ match threshold value |
| irq_match | Output | 1 | IRQ match flag |
| sticky_overflow | Output | 1 | Sticky overflow flag |
Verification
The testbench validates reset behavior, load functionality, counting sequence, match IRQ, and sticky overflow. All test cases passed successfully in the Icarus Verilog simulation environment.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Reset clears counter, sticky overflow, and IRQ match | PASS |
| TC2 | Load specific value and verify IRQ is not asserted | PASS |
| TC3 | Count to match value and verify IRQ assertion/clearing | PASS |
| TC4 | Count to overflow and verify sticky overflow flag | PASS |
| TC5 | Load new value and verify sticky overflow is cleared | PASS |
More in Counters
- 16-Bit Cycle Counter with Prescaler — L1 Upgrade — L2 Upgrade
- 4-Bit Counter Match Pulse
- 4-Bit Counter with Wrap Strobe
- 4-Bit Down Counter
- 4-Digit BCD Up/Down Counter with Carry/Borrow
- 8-Bit Binary Up Counter — L1 Upgrade — L2 Upgrade
- 8-Bit Johnson Counter (Twisted Ring) — L1 Upgrade — L2 Upgrade
- 8-Bit Leading Zero Counter — L1 Upgrade — L2 Upgrade
- 8-Bit Ring Counter
- 8-Bit Up/Down Counter
- Bidirectional Counter 4-Bit — L1 Upgrade — L2 Upgrade
- Decade BCD Counter 1-Digit — L1 Upgrade
- Dual Compare-Match Counter 8 — L1 Upgrade — L2 Upgrade
- Event Counter with Capture
- Gray-Code Counter 8-Bit — L2 Upgrade
- Loadable 4-Bit Up Counter