Memory & FIFOs

Asymmetric RAM WR8 RD16 — L2 Upgrade

Asymmetric RAM with 8-bit write, 16-bit read, byte-enable, and invalidate-to-shadow functionality.

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Asymmetric RAM WR8 RD16 — L2 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an asymmetric RAM module with 8-bit write and 16-bit read capabilities. It is designed for L2 cache upgrades or buffer management scenarios where the read width exceeds the write width.

Key features include:

Byte-Enable Controls: Precise targeting of lower (byte_en[0]) or upper (byte_en[1]) bytes during writes.
Invalidate Mechanism: Allows switching read data from the active memory to a shadow memory.
Shadow Memory Persistence: When an address is invalidated, the active memory data is hidden, and reads return data from the shadow memory. The shadow memory retains the last valid data written to that address before invalidation.
Synchronous Operation: Fully synchronous reset and clocked logic.
Ready Signal: An always-high status signal indicating the module is ready for operations.

This IP provides a robust asymmetric RAM solution for systems requiring 8-bit writes and 16-bit reads. It includes sophisticated control features like byte-enable targeting and an invalidate/shadow mechanism for data persistence and cache-like behavior. The design is fully synchronous, easy to integrate, and thoroughly verified.

Choose Open in IDE. RTL Studio loads the packaged workspace for Asymmetric RAM WR8 RD16 — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Asymmetric RAM with 8-bit write, 16-bit read, byte-enable, and invalidate-to-shadow functionality.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Memory Depth & Width: 16-word deep memory array with 16-bit width.
Asymmetric Interface: 8-bit write data input (wr_data), 16-bit read data output (rd_data).
Byte-Enable Controls: Independent targeting of lower (byte_en[0]) or upper (byte_en[1]) bytes.
Invalidate Feature: Switches read data from active memory to shadow memory via inv_en.
Shadow Memory: Retains data when active memory is invalidated; updated on write.
Synchronous Operation: Synchronous reset (rst_n) and clocked logic.
Ready Signal: Always-high status signal for simple handshaking.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`wr_en`	Input	1	Write enable
`rd_en`	Input	1	Read enable
`inv_en`	Input	1	Invalidate enable
`byte_en`	Input	2	Byte enable [1:0] (0: lower, 1: upper)
`wr_data`	Input	8	Write data input
`addr`	Input	4	Address input (0-15)
`rd_data`	Output	16	Read data output
`ready`	Output	1	Ready status (always high)

Verification

The testbench verifies basic write operations to lower and upper bytes, read-back data integrity for 16-bit wide reads, and the invalidate functionality against shadow memory fallback. It ensures byte-enable zero does not alter existing data and confirms the ready signal remains high during operation.

### Test Cases

Test Case	Description	Result
TC1	Write 8-bit to Lower Byte, Read 16-bit	PASS
TC2	Write 8-bit to Upper Byte, Read 16-bit	PASS
TC3	Invalidate and Read Shadow	PASS
TC4	Restore Shadow via Write	PASS
TC5	Byte Enable 00 No Change	PASS
TC6	Ready Signal High	PASS

### Expected Simulation Results

After running the simulation, the Log panel should display:

TC1 PASS
TC2 PASS
TC3 PASS
TC4 PASS
TC5 PASS
TC6 PASS
INFO: PASS

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