Memory & FIFOs

16×8 Sync RAM (No Reset, Registered Read) — L2 Upgrade

16-word by 8-bit synchronous RAM with independent write/read clocks and registered read output. No reset logic included.

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Hardverilogsimsyn

16×8 Sync RAM (No Reset, Registered Read) — L2 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a 16-word by 8-bit synchronous RAM with registered read output. It supports independent write and read clock domains for multi-clock operation. The design explicitly omits reset logic to meet specific low-latency or area-constrained requirements. Read data is registered on the read clock edge to ensure stable output timing.

This IP provides a simple, multi-clock synchronous RAM with registered read output. It is suitable for designs requiring independent clock domains for write and read operations. The lack of reset simplifies the logic but requires careful initialization in the system context.

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Read the Verilog module in the editor. The catalog line for this block: 16-word by 8-bit synchronous RAM with independent write/read clocks and registered read output. No reset logic included.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Capacity: 16 words × 8 bits.
Write port: Synchronous write enabled by we_w on clk_w.
Read port: Synchronous read with registered output on clk_r.
Multi-clock domain: Write and read clocks are independent.
No reset: The memory content is uninitialized on power-up (simulators typically default to 0).
Registered read: Output data_r is stable one cycle after the read address is asserted.

Ports

Port Name	Direction	Width	Description
`clk_w`	Input	1	Write clock domain
`rst_w_n`	Input	1	Write reset (unused in logic, kept for interface consistency)
`addr_w`	Input	4	Write address [3:0]
`data_w`	Input	8	Write data [7:0]
`we_w`	Input	1	Write enable
`clk_r`	Input	1	Read clock domain
`rst_r_n`	Input	1	Read reset (unused in logic, kept for interface consistency)
`addr_r`	Input	4	Read address [3:0]
`data_r`	Output	8	Read data [7:0]

Architecture

The design consists of a single synchronous memory array and a registered output stage. The write logic updates the memory array only when we_w is high on the rising edge of clk_w. The read logic samples the memory content on the rising edge of clk_r and registers it. This registered read approach helps in timing closure by moving the output flip-flops closer to the load.

Verification

The testbench verifies single write/read, multi-address operations, overwrite behavior, and boundary conditions. All test cases passed successfully in the Icarus Verilog simulation.

Test Case	Description	Result
TC1	Write 0xAA to address 0 and read back	PASS
TC2	Write to addresses 1-3 and read back sequentially	PASS
TC3	Overwrite address 0 with 0xBB and verify	PASS
TC4	Write to last address (15) and read back	PASS

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