Memory & FIFOs

16-Word 16-Bit Sync RAM with Byte Enable — L2 Upgrade

A 16-word by 16-bit synchronous RAM with independent write/read clocks and 2-bit byte enable support. Features active-low reset and registered read output for timing closure.

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16-Word 16-Bit Sync RAM with Byte Enable — L2 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a 16-word by 16-bit synchronous RAM with independent write and read clocks (dual-clock operation).

It supports partial word updates via a 2-bit byte enable signal (be[1:0]).

The read port is registered to ensure timing closure.

Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Word 16-Bit Sync RAM with Byte Enable — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 16-word by 16-bit synchronous RAM with independent write/read clocks and 2-bit byte enable support. Features active-low reset and registered read output for timing closure.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Depth: 16 words
Width: 16 bits
Clocks: Separate clk_w (write) and clk_r (read)
Byte Enable: Supports independent control of lower 8 bits (be[0]) and upper 8 bits (be[1])
Reset: Active-low rst_n clears all memory to zero
Read Output: Registered output on clk_r edge

Architecture

The memory array consists of 16 registers, each 16 bits wide.

### Write Port

Sensitive to clk_w and rst_n.
Writes occur on the rising edge of clk_w when we is asserted.
Byte enable be[0] controls the lower 8 bits of the data word.
Byte enable be[1] controls the upper 8 bits of the data word.
Unselected bytes retain their previous values during a write operation.

### Read Port

Sensitive to clk_r.
Reads occur on the rising edge of clk_r when re is asserted.
The output data_out is registered to match the read clock domain.

Ports

Port Name	Direction	Width	Description
`clk_w`	Input	1	Write clock input
`clk_r`	Input	1	Read clock input
`rst_n`	Input	1	Active-low reset input
`addr_w`	Input	4	Write address bus
`addr_r`	Input	4	Read address bus
`data_in`	Input	16	Write data bus
`be`	Input	2	Byte enable bus [1:0]
`we`	Input	1	Write enable signal
`re`	Input	1	Read enable signal
`data_out`	Output	16	Read data bus

Integration

### Directory Structure

### Simulation To verify the design, run the testbench using Icarus Verilog:

### Expected Results After running the simulation, the Log panel should show:

TC1 Full Word Write/Read PASS
TC2 Byte Enable Low Byte PASS
TC2 Byte Enable High Byte preservation PASS
TC3 Byte Enable High Byte PASS
TC3 Byte Enable Low Byte preservation PASS
TC4 Reset Clear PASS
TC5 Dual Clock Independence PASS
TC6 Boundary Addr 0 PASS

Verification

The testbench verifies the following scenarios:

Test Case	Description	Result
TC1	Full Word Write and Read	PASS
TC2	Byte Enable Low Byte Write	PASS
TC3	Byte Enable High Byte Write	PASS
TC4	Reset Clears Memory	PASS
TC5	Dual Clock Independence	PASS
TC6	Boundary Addresses (0 and 15)	PASS

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