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Memory & FIFOs

4x8 1W1R Register File (Comb Read)

A 4-deep by 8-bit wide register file with synchronous write and combinational read ports.

Open in IDE Category Wiki · memories

About this block

Simulate it in the Verilog IDE

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4x8 1W1R Register File (Comb Read) is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 4-deep by 8-bit wide register file with 1 Write port and 1 Read port. It is designed for small on-chip storage requirements where low-latency reads are critical.

This IP provides a lightweight, combinational-read register file suitable for low-latency applications. It features synchronous writing, asynchronous reset, and a simple interface. The design is fully verified with a testbench that checks reset behavior, write/read integrity, and data persistence.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 4x8 1W1R Register File (Comb Read).
  2. Read the Verilog module in the editor. The catalog line for this block: A 4-deep by 8-bit wide register file with synchronous write and combinational read ports.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design consists of a simple memory array (mem[0:3]) of 8-bit registers.

  • Write Logic: On the positive edge of clk, if we is high, the value on din is written to the address specified by waddr.
  • Read Logic: The output dout is directly assigned to mem[raddr], providing zero-latency combinational read.
  • Reset Logic: When rst_n is low, all memory elements are asynchronously cleared to 0.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input for synchronous write
rst_nInput1Active-low asynchronous reset
weInput1Write enable signal
waddrInput2Write address (0-3)
dinInput8Data input for write
raddrInput2Read address (0-3)
doutOutput8Data output from read

Verification

The provided testbench (tb/tb_regfile_4x8_1w1r_comb_read.v) verifies the following behaviors:

  1. Reset: Ensures all registers initialize to zero upon assertion of rst_n.
  2. Write/Read Integrity: Writes specific values to addresses 0, 1, and 3, and reads them back to verify data integrity.
  3. Unwritten Address: Verifies that unwritten addresses (e.g., address 2) remain zero.
  4. Persistence: Confirms that written data persists across multiple clock cycles.

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