Memory & FIFOs

8×8 Sync RAM (Async Reset, Comb Read, Loop Init) — L1 Upgrade

8-bit wide, 8-depth synchronous single-port RAM with write-first read behavior and asynchronous reset.

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About this block

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Mediumverilogsimsyn

8×8 Sync RAM (Async Reset, Comb Read, Loop Init) — L1 Upgrade is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a simple, efficient 8-bit wide, 8-depth synchronous single-port RAM. It features a write-first read behavior, where the output updates with the written data in the same clock cycle. The design uses an asynchronous active-low reset to initialize the output register to zero. Read operations are registered at the output, ensuring stable timing.

This IP is suitable for small on-chip buffers where immediate data availability after a write is required. The design is fully synthesizable and verified with Icarus Verilog.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8×8 Sync RAM (Async Reset, Comb Read, Loop Init) — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit wide, 8-depth synchronous single-port RAM with write-first read behavior and asynchronous reset.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Interface

The module exposes a standard single-port RAM interface.

Signal	Direction	Width	Description
clk	input	1	Clock input
rst_n	input	1	Asynchronous active-low reset
addr	input	3	Address input (0-7)
din	input	8	Data input
we	input	1	Write enable
dout	output	8	Data output

Architecture

The memory array is defined as an 8x8 register file. The output register captures the new data immediately when we is asserted. This ensures write-first behavior where dout reflects the written value before the next clock edge.

On read cycles (we low), dout reflects the current content of the addressed memory location. The asynchronous reset forces dout to 8'h00 regardless of the clock state.

Verification

The testbench verifies reset behavior and write-first/read logic. All six test cases passed successfully.

Test Case	Description	Result
TC1	Reset output is zero	PASS
TC2	Write-first at addr 0	PASS
TC3	Read addr 0 after write	PASS
TC4	Write-first at addr 7	PASS
TC5	Read addr 7 after write	PASS
TC6	Read addr 0 after write to 7	PASS

### Expected Simulation Output

After running the simulation, the Log panel should show:

INFO: TC1 PASS Reset output is zero
INFO: TC2 PASS Write-first at addr 0
INFO: TC3 PASS Read addr 0
INFO: TC4 PASS Write-first at addr 7
INFO: TC5 PASS Read addr 7
INFO: TC6 PASS Read addr 0 after write to 7
INFO: PASS

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