Memory & FIFOs
32-Bit Register with Byte Writes
A 32-bit register with independent byte-write enables for partial updates.
About this block
Simulate it in the Verilog IDE
32-Bit Register with Byte Writes is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP implements a 32-bit register with independent byte-write enables. It allows partial updates to the register without affecting other bytes. The module is suitable for memory-mapped I/O or configuration registers.
This IP provides a simple and efficient byte-writeable 32-bit register. It is verified with a comprehensive self-checking testbench. The design is synthesizable and ready for integration.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit Register with Byte Writes.
- Read the Verilog module in the editor. The catalog line for this block: A 32-bit register with independent byte-write enables for partial updates.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
Supports 32-bit data width. Provides 4-bit write enable signal for byte-level control. Synchronous reset to zero. Positive clock edge triggered.
Ports
| Port | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock input |
| rst_n | Input | 1 | Active-low reset |
| we | Input | 4 | Write enable per byte [3:0] |
| din | Input | 32 | Data input |
| dout | Output | 32 | Data output |
Verification
The testbench performs self-checking verification. It covers reset behavior and individual byte writes. It verifies partial writes preserve upper bytes. It verifies all-byte writes overwrite the full register.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Reset check | PASS |
| TC2 | Byte 0 write | PASS |
| TC3 | Byte 1 write | PASS |
| TC4 | Byte 2 write | PASS |
| TC5 | Byte 3 write | PASS |
| TC6 | All bytes write | PASS |
| TC7 | Partial write | PASS |
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