Memory & FIFOs

Circular Buffer 16x8

A synchronous circular buffer with 16 entries and 8-bit data width supporting push/pop operations with full/empty flags.

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About this block

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Circular Buffer 16x8 is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

A synchronous circular buffer IP core with 16 entries and 8-bit data width. Designed for high-throughput data streaming applications, it supports push and pop operations with robust full/empty status flags and registered read output for stable timing.

This IP provides a robust 16x8 circular buffer for data streaming applications. It ensures data integrity through proper pointer management and flag control. The registered read output simplifies downstream timing analysis by stabilizing data_out on the clock edge.

Choose Open in IDE. RTL Studio loads the packaged workspace for Circular Buffer 16x8.
Read the Verilog module in the editor. The catalog line for this block: A synchronous circular buffer with 16 entries and 8-bit data width supporting push/pop operations with full/empty flags.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Capacity: 16 entries of 8-bit data.
Operations: Synchronous push and pop (Level-sensitive control signals).
Status Flags:

- full: Asserted when the buffer is at maximum capacity (16 items). - empty: Asserted when the buffer is empty (0 items). - count: Provides the current number of valid items (0-15).

Pointer Management: Automatic wrap-around for write and read pointers.
Registered Output: data_out is registered to ensure stable timing for downstream logic.
Reset: Active-low synchronous reset (rst_n).

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`push`	Input	1	Push command (write data). Must be deasserted if `full` is high.
`pop`	Input	1	Pop command (read data). Must be deasserted if `empty` is high.
`data_in`	Input	8	Data to write
`data_out`	Output	8	Data read from buffer (registered)
`full`	Output	1	Buffer is full
`empty`	Output	1	Buffer is empty
`count`	Output	4	Number of items (0-15)

Verification

The testbench verifies reset state, basic push/pop, full/empty flags, and wrap-around integrity. All 16 test cases passed successfully in the simulation log. The simulation was run using Icarus Verilog. VCD dump is available for waveform inspection.

Test Case	Description	Result
TC1	Reset State	PASS
TC2	Basic Push/Pop	PASS
TC3	Full/Empty Flags	PASS
TC4	Wrap Around	PASS

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