Memory & FIFOs
8x16 Single-Port Sync RAM
8x16 Single-Port Synchronous RAM with byte write enable. Depth: 8 words, Width: 16 bits. Read is synchronous (data available on next clock edge after address). Write is synchronous (data written on rising edge if we_n is low).
About this block
Simulate it in the Verilog IDE
8x16 Single-Port Sync RAM is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This 8x16 single-port synchronous RAM is ideal for small, fast on-chip storage requirements.
It supports byte-level write granularity for efficient data manipulation.
The synchronous read latency of one cycle simplifies timing analysis in pipelined designs.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 8x16 Single-Port Sync RAM.
- Read the Verilog module in the editor. The catalog line for this block: 8x16 Single-Port Synchronous RAM with byte write enable. Depth: 8 words, Width: 16 bits. Read is synchronous (data available on next clock edge after address). Write is synchronous (data written on rising edge if we_n is low).
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Interface
The module exposes a standard synchronous interface with the following signals.
| Signal | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock input for synchronous operations. |
| rst_n | Input | 1 | Active-low asynchronous reset signal. |
| addr | Input | 3 | Address input selecting one of the 8 memory locations. |
| din | Input | 16 | Data input for write operations. |
| we_n | Input | 1 | Active-low write enable; low triggers a write on the clock edge. |
| be | Input | 2 | Byte enable mask; 2'b01 writes lower byte, 2'b10 writes upper byte, 2'b11 writes both. |
| dout | Output | 16 | Data output registered on the clock edge corresponding to the address input. |
Architecture
The design uses an internal register array to store the 8x16 memory content. A separate output register ensures synchronous read behavior by delaying the data by one clock cycle. Byte enable logic allows partial word updates without affecting the other byte lanes.
Verification
The provided testbench covers reset behavior, basic read/write cycles, byte enable masking, and back-to-back access patterns. All tests passed successfully during simulation with Icarus Verilog.
| Test Case | Description | Result |
|---|---|---|
| TC1 | Reset Test | PASS |
| TC2 | Basic Write and Read | PASS |
| TC3 | Byte Enable Test | PASS |
| TC4 | Back-to-Back Access | PASS |
More in Memory & FIFOs
- 16-Word 16-Bit Sync RAM with Byte Enable — L2 Upgrade
- 16×8 Sync RAM (No Reset, Registered Read) — L2 Upgrade
- 32-Bit Asynchronous FIFO with Gray Pointer Encoding
- 32-Bit Register with Byte Writes
- 32x16 Synchronous Single-Port RAM
- 4x8 1W1R Register File (Comb Read)
- 4×8 Sync RAM (Async Reset, Comb Read)
- 64-bit Wide Scratchpad RAM with Dual-Port Access
- 8-Bit Valid/Ready Skid Buffer
- 8x32 Dual-Read Register File
- 8×8 Sync RAM (Async Reset, Comb Read, Loop Init) — L1 Upgrade
- Asymmetric RAM WR8 RD16 — L2 Upgrade
- Byte-Enable Regfile 8x32 — L2 Upgrade
- CAM 4x8 with Invalidate
- Circular Buffer 16x8
- Count-Based Sync FIFO with Dual Ready/Valid