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Memory & FIFOs

64-bit Wide Scratchpad RAM with Dual-Port Access

256x64 dual-port RAM with byte-enable masking and combinational reads.

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About this block

Simulate it in the Verilog IDE

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64-bit Wide Scratchpad RAM with Dual-Port Access is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP provides a 256-entry, 64-bit wide dual-port scratchpad RAM. It supports independent byte-enable masking for both read/write ports. Port A and Port B operate concurrently with separate address and data buses.

This scratchpad RAM offers a simple, high-performance dual-port memory solution for on-chip data storage. Integrators should note that read outputs are zero when disabled, which simplifies bus tri-state management. Byte enables allow efficient partial word updates without read-modify-write cycles. The lack of memory reset means initial power-up values are undefined and should be handled by software.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 64-bit Wide Scratchpad RAM with Dual-Port Access.
  2. Read the Verilog module in the editor. The catalog line for this block: 256x64 dual-port RAM with byte-enable masking and combinational reads.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The following diagram illustrates the internal structure and data flow of the dual-port scratchpad RAM.

Features

  • Depth & Width: 256 x 64-bit memory depth.
  • Dual Ports: Independent Port A and Port B for concurrent access.
  • Byte Enables: 8-bit byte enables (be_a, be_b) for granular write control.
  • Read Latency: Combinational read path for low latency.
  • Write Latency: Synchronous write path triggered on the positive clock edge.
  • Reset Behavior: Global reset (rst_n) does not clear memory content; data is retained.

Verification

The provided testbench verifies:

  • Basic write/read operations for both ports.
  • Byte-enable masking functionality.
  • Concurrent access with different addresses.
  • Concurrent access to the same address.
  • Port disabling logic (zero output when ce is inactive).

All six test cases passed successfully in simulation.

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