Memory & FIFOs

8x32 Dual-Read Register File

An 8-deep, 32-bit wide register file with one synchronous write port and two independent combinational read ports.

Open in IDE Category Wiki · memories

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

8x32 Dual-Read Register File is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements an 8x32 dual-read register file, featuring one synchronous write port and two independent combinational read ports.

It is designed for low-latency data storage and forwarding in digital pipelines.

The core supports asynchronous active-low reset and ensures predictable timing through combinational reads.

Depth: 8 words
Width: 32 bits
Write Port: 1 synchronous port (active on positive clock edge)
Read Ports: 2 independent combinational ports
Reset: Asynchronous, active-low

Choose Open in IDE. RTL Studio loads the packaged workspace for 8x32 Dual-Read Register File.
Read the Verilog module in the editor. The catalog line for this block: An 8-deep, 32-bit wide register file with one synchronous write port and two independent combinational read ports.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The internal memory array is 8-deep by 32-bit wide. Write operations are synchronous to the positive clock edge when wr_en is asserted. Read operations are combinational, meaning rd_data is available immediately upon address change.

Ports

Signal Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Asynchronous active-low reset
`wr_addr`	Input	3	Write address bus
`wr_data`	Input	32	Write data bus
`wr_en`	Input	1	Write enable signal
`rd_addr_a`	Input	3	Read address bus for Port A
`rd_data_a`	Output	32	Read data output for Port A
`rd_addr_b`	Input	3	Read address bus for Port B
`rd_data_b`	Output	32	Read data output for Port B

Integration

To integrate this IP into your design, instantiate the module as follows:

Verification

The included testbench (tb_register_file_8x32.v) performs comprehensive self-checking verification.

### Test Cases

Test Case	Description	Result
TC1	Reset Check	PASS
TC2	Write/Read Port A	PASS
TC3	Write/Read Port B	PASS
TC4	Overwrite/Independence	PASS
TC5	Boundary Addresses	PASS

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