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Memory & FIFOs

4×8 Sync RAM (Async Reset, Comb Read)

Four-word 8-bit single-port RAM with async reset clear, synchronous write, and combinational read.

Open in IDE Category Wiki · memories

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

4×8 Sync RAM (Async Reset, Comb Read) is a Verilog reference block in the Memory & FIFOs catalog. SRAM models, FIFOs, register files, and memory-style storage. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

A simple 4-word, 8-bit synchronous RAM module with combinational read and asynchronous reset.

This IP provides a minimal synchronous RAM block suitable for small on-chip buffering or state storage. It features:

  • Depth: 4 words
  • Width: 8 bits
  • Write: Synchronous (positive clock edge)
  • Read: Combinational (zero latency)
  • Reset: Asynchronous, active-low
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 4×8 Sync RAM (Async Reset, Comb Read).
  2. Read the Verilog module in the editor. The catalog line for this block: Four-word 8-bit single-port RAM with async reset clear, synchronous write, and combinational read.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design uses a Verilog register array. Writes occur only when we is high on the rising edge of clk. Reads are continuous assignments, providing immediate access to the stored data.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input for synchronous operations.
rst_nInput1Active-low asynchronous reset.
addrInput2Address input (0-3).
weInput1Write enable. High enables write on clock edge.
dinInput8Data input for write operations.
doutOutput8Data output for read operations.

Verification

The included testbench (tb_sync_ram_4x8.v) verifies:

  1. Basic write/read functionality for all 4 addresses.
  2. Data persistence (data remains unchanged when writing to other addresses).

### Running Simulation

To run the simulation, use your preferred Verilog simulator (e.g., Icarus Verilog):

Expected Output:

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